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0.5c accurate digital temperature sensor and quad voltage output 12-/10-/8-bit dacs adt7316/adt7317/adt7318 rev . a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures adt73 16fou r 12-bit dacs adt73 17fou r 10-bit dacs adt73 18fou r 8-bit d a cs buffered volta g e output guarantee d m o notonic by de sign over all codes 10-bit tempera t ure-to-digita l converter temperature r a nge: ?40 c to +120 c temperature s e nsor a ccu racy of 0.5c supply range: 2.7 v to 5.5 v dac o u tp ut ra nge: 0 v to 2 v re f power-down current 1 a internal 2.28 v re f option do uble-buffer e d input lo gic buffered/unbuffered r e ferenc e input option power-on reset to 0 v simultaneo us update o f o u tp uts ( ldac function) on-chip rail-to-rail output buff er amplifier i 2 c?, smbus, spi?, qspi?, microwire?, and dsp compatible 4-wire seri al in terface smbus packet error checking (pec) compatible 16-lea d qsop package applic ati o ns portable batter y -powered inst ruments personal computers telecommunications systems electronic test equipment domestic appliances process control pin c o nfig ur a t ion 02661-a - 006 adt7316/ adt7317/ adt7318 top view (not to scale) v out -b 1 v out -c 16 v out -a 2 v out -d 15 v ref -ab 3 v ref -cd 14 cs 4 scl/sclk 13 gnd 5 sda/din 12 v dd 6 dout/add 11 d+ 7 int/int 10 d? 8 ldac 9 fi g u r e 1 . gener a l description the adt7316 /adt7317/ad t7318 1 co m b in e a 10-b i t t e m p - era t ur e-t o -dig i t al co n v er t e r and a q u ad 12-/10-/8-b i t d a c, re sp e c t i v e ly , i n a 1 6 - l e a d q s op p a ckage. this i n cl u d e s a b a nd ga p tem p er a t ure s e n s o r and a 1 0 -b i t ad c to mo ni to r an d dig i t i ze t h e t e m p era t ur e r e ad ing t o a r e s o l u t i o n o f 0.25c. t h e adt7316/ad t7317/adt7318 o p era t e f r o m a s i n g le 2.7 v t o 5.5 v s u p p l y . th e o u t p ut v o l t a g e o f t h e d a c ran g es f r o m 0 v t o 2 v ref , w i t h a n outpu t v o lt a g e s e tt l i ng t i me of t y p 7 ms . t h e adt7316/ad t7317/adt7318 p r o v ide tw o s e r i al in t e r f ace o p ti o n s, a 4-w i r e se rial in t e rfa c e th a t i s co m p a t i b le wi th s p i, qs pi, mi cro w ire, and ds p in ter f a c e st and a r d s, a nd a 2- w i r e sm b u s / i 2 c i n t e r f ace. t h e y fe a t ur e a st andb y mo de t h a t is co n t r o ll ed via t h e se rial in t e rface . the r e fer e n c e fo r t h e fo ur d a cs is der i v e d ei t h er i n t e r n al l y or f r om t w o re fe renc e pi ns ( o ne p e r d a c p a i r ) . t h e output s of a l l d a c s ma y b e u p da t e d s i m u l t a n eo us l y us i n g th e so ft w a r e ld a c fu n c ti o n o r e x t e rn al ld a c p i n. th e ad t7316/adt7 317/ adt7318 in co r p o r a t e a p o w e r - o n -r es et c i r c ui t tha t ens u r e s t h e d a c o u t p u t p o w e rs u p to 0 v and r e ma in s t h er e un t i l a va l i d wr i t e t a k e s plac e . the adt7316 /adt7317/ad t7318 s wide su p p l y v o l t a g e ra n g e , l o w su p p ly c u r r e n t, and s p i / i 2 c co m p a t i b l e i n t e rfa c e m a k e th em id eal f o r a v a ri e t y o f a p p l ica t i o n s , in c l ud in g pe r s o n al co m p u t ers, o f f i ce e q ui pmen t, and dom e st ic a pplian c es. 1 p r ot ec t e d by the f o llowing u . s. pa t e nt nu mbers: 5, 76 4 , 174; 5, 86 7, 01 2; 6, 097, 2 39; 6, 1 69, 4 42. o t her pa t e nts pending .
adt7316/adt7317/adt7318 rev. a | page 2 of 40 table of contents specifications ..................................................................................... 3 functional block diagram .............................................................. 7 dac ac characteristics .................................................................. 8 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 ter mi nolo g y .................................................................................... 11 typical performance characteristics ........................................... 13 theory of operation ...................................................................... 18 power-up calibration ................................................................ 18 conversion speed ....................................................................... 18 functional descriptionvoltage output ................................... 19 digital-to-analog converters ................................................... 19 digital-to-analog section ......................................................... 19 resistor string ............................................................................. 19 dac external reference inputs ............................................... 19 output amplifier ........................................................................ 20 thermal voltage output ............................................................ 20 functional descriptionmeasurement ...................................... 22 temperature sensor ................................................................... 22 v dd monitoring .......................................................................... 22 on-chip reference .................................................................... 23 round robin measurement ...................................................... 23 single-channel measurement .................................................. 23 temperature measurement method ........................................ 23 temperature value format ....................................................... 24 interrupts ..................................................................................... 25 registers ........................................................................................... 26 serial interface ................................................................................ 34 serial interface selection ........................................................... 34 i 2 c serial interface ..................................................................... 34 spi serial interface ..................................................................... 35 layout considerations ................................................................... 39 outline dimensions ....................................................................... 40 ordering guide .......................................................................... 40 revision history 6/04data sheet changed from rev. 0 to rev. a updated format...................................................................... universal internal v ref value change ................................................... universal change to equation in thermal voltage output section ..............21 changes to outline dimensions........................................................40 8/03initial version: rev.0
adt7316/adt7317/adt7318 rev. a | page 3 of 40 specifications table 1. temperature ranges are as fo llows: a version: C40c to +120c. v dd = 2.7 v to 5.5 v, gnd = 0 v, ref in = 2.25 v, unless otherwise noted. parameter 1 min typ max unit conditions/comments dac dc performance 2 , 3 adt7318 resolution 8 bits relative accuracy 0.15 1 lsb differential nonlinearity 0.02 0.25 lsb guaranteed monotonic over all codes. adt7317 resolution 10 bits relative accuracy 0.5 4 lsb differential nonlinearity 0.05 0.5 lsb guaranteed monotonic over all codes. adt7316 resolution 12 bits relative accuracy 2 16 lsb differential nonlinearity 0.02 0.9 lsb guaranteed monotonic over all codes. offset error 0.4 2 % of fsr gain error 0.4 2 % of fsr lower dead band 20 65 mv lower dead band exists only if offset error is negative. see figure 2. upper dead band 60 100 mv upper dead band exists if v ref = v dd and offset plus gain error is positive. see figure 3 . offset error drift ? 12 ppm of fsr/c gain error drift ? 5 ppm of fsr/c dc power supply rejection ratio ? 60 db ? v dd = 10%. dc crosstalk 200 v see figure 6 . thermal characteristics internal temperature sensor internal reference used. averaging on. accuracy at v dd = 3.3 v 10% 1.5 c t a = 85c. 0.5 3 c t a = 0c to +85c. 2 5 c t a = ? 40c to +120c. accuracy at v dd = 5 v 5% 2 3 c t a = 0c to +85c. 3 5 c t a = ? 40c to +120c. resolution 10 bits equivalent to 0.25c. long term drift 0.25 c drift over 10 years if part is operated at 55c. external temperature sensor external transistor = 2n3906. accuracy at v dd = 3.3 v 10% 1.5 c t a = 85c. 3 c t a = 0c to +85c. 5 c t a = ? 40c to +120c. accuracy at v dd = 5 v 5% 2 3 c t a = 0c to +85c. 3 5 c t a = ? 40c to +120c. resolution 10 bits equivalent to 0.25c. output source current 180 a high level. 11 a low level. thermal voltage output 8-bit dac output resolution 1 c scale factor 8.79 mv/c 0 v to v ref output. t a = ? 40c to +120c. 17.58 mv/c 0 v to 2 v ref output. t a = ? 40c to +120c. 1 see . terminology 2 dc specifications tested with the outputs unloaded. 3 linearity is tested using a reduced code range: adt7316 (code 115 to 4095); adt7317 (code 28 to 1023); adt7318 (code 8 to 255).
adt7316/adt7317/adt7318 rev. a | page 4 of 40 parameter 1 min typ max unit conditions/comments 10-bit dac output resolution 0.25 c scale factor 2.2 mv/c 0 v to v ref output. t a = ? 40c to +120c. 4.39 mv/c 0 v to 2 v ref output. t a = ? 40c to +120c. conversion times single channel mode. slow adc v dd 11.4 ms averaging (16 samples) on. 712 s averaging off. internal temperature 11.4 ms averaging (16 samples) on. 712 s averaging off. external temperature 24.22 ms averaging (16 samples) on 1.51 ms averaging off. fast adc v dd 712 s averaging (16 samples) on. 44.5 s averaging off. internal temperature 2.14 ms averaging (16 samples) on. 134 s averaging off. external temperature 14.25 ms averaging (16 samples) on. 890 s averaging off. round robin update rate 4 time to complete one measurement cycle through all channels. slow adc at 25c averaging on 59.95 ms averaging off 6.52 ms fast adc at 25c averaging on 19.59 ms averaging off 2.89 ms dac external reference input 5 v ref input range 1 v dd v buffered reference mode. v ref input range 0.25 v dd v unbuffered reference mode. v ref input impedance 37 45 k ? unbuffered reference mode. 0 v to 2 v ref output range. 74 90 k ? unbuffered reference mode. 0 v to v ref output range. >10 m ? buffered reference mode and power-down mode. reference feedthrough ? 90 db frequency = 10 khz. channel-to-channel isolation ? 75 db frequency = 10 khz. on-chip reference reference voltage 5 2.28 v temperature coefficient 5 80 ppm/c output characteristics 5 output voltage 6 0.001 v dd to 0.001 v this is a measure of the minimum and maximum drive capability of the output amplifier. dc output impedance 0.5 ? short circuit current 25 ma v dd = 5 v. 16 ma v dd = 3 v. power-up time 2.5 s coming out of power-down mode. v dd = 5 v. 5 s coming out of power-down mode. v dd = 3.3 v. 4 round robin is the continuous sequential measurement of the following three channels: v dd , internal temperature, an d external temperature. 5 guaranteed by design and characterization, but not production tested. 6 in order for the amplifier output to reach its minimum voltage, the offset error must be negative. in order for the amplifier o utput to reach its maximum voltage, v ref = v dd , offset plus gain error must be positive.
adt7316/adt7317/adt7318 rev. a | page 5 of 40 parameter 1 min typ max unit conditions/comments digital inputs 5 input current 1 a v in = 0 v to v dd . input low voltage, v il 0.8 v input high voltage, v ih 1.89 v pin capacitance 3 10 pf all digital inputs. scl, sda glitch rejection 50 ns input filter ing suppresses noise spikes of less than 50 ns. ldac pulse width 20 ns edge triggered input. digital output output high voltage, v oh 2.4 v i source = i sink = 200 a. output low voltage, v ol 0.4 v i ol = 3 ma. output high current, i oh 1 ma v oh = 5 v. output capacitance, c out 50 pf int/ int output saturation voltage 0.8 v i out = 4 ma. i 2 c timing characteristics 7 , 8 serial clock period, t 1 2.5 s fast-mode i 2 c. see figure 4 . data in setup time to scl high, t 2 50 ns data out stable after scl low, t 3 0 ns see figure 4 . sda low setup time to scl low (start condition), t 4 50 ns see figure 4 . sda high hold time after scl high (stop condition), t 5 50 ns see figure 4 . sda and scl fall time, t 6 90 ns see figure 4 . spi timing characteristics 9 , 10 cs to sclk setup time, t 1 0 ns see figure 7 . sclk high pulse width, t 2 50 ns see figure 7 . sclk low pulse, t 3 50 ns see figure 7 . data access time after sclk falling edge, t 4 11 35 ns see figure 7 . data setup time prior to sclk rising edge, t 5 20 ns see figure 7 . data hold time after sclk rising edge, t 6 0 ns see figure 7 . cs to sclk hold time, t 7 0 ns see figure 7 . cs to dout high impedance, t 8 40 ns see figure 7 . power requirements v dd 2.7 5.5 v v dd settling time 50 ms v dd settles to within 10% of its final voltage level. i dd (normal mode) 12 3 ma v dd = 3.3 v, v ih = v dd and v il = gnd. 2.2 3 ma v dd = 5 v, v ih = v dd and v il = gnd. i dd (power down mode) 10 a v dd = 3.3 v, v ih = v dd and v il = gnd. 10 a v dd = 5 v, v ih = v dd and v il = gnd. power dissipation 10 mw v dd = 3.3 v. using normal mode. 33 w v dd = 3.3 v. using shutdown mode. 7 the sda and scl timing is measured with the input fi lters turned on so as to meet the fast-mode i 2 c specification. switching off the input filters improves the transfer rate but has a negative effect on the emc behavior of the part. 8 guaranteed by design. not tested in production. 9 guaranteed by design and characterization, but not production tested. 10 all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. 11 measured with the load circuit of . figure 5 12 i dd specification is valid for all dac codes. interface inactive. all dacs active. load currents excluded.
adt7316/adt7317/adt7318 r e v. a | pa ge 6 o f 4 0 amplifier footroom lower deadband codes negative offset error gain error + offset error actual output voltage negative offset error dac code ideal 02661-a - 007 f i gure 2 . d a c t r a n s f er f u nctio n wi th nega ti v e o ffset 02661-a - 008 actual gain error + offset error upper deadband codes output voltage positive offset error dac code full scale ideal f i gure 3 . d a c t r a n s f er f u nctio n wi th p o si ti v e o ffset ( v re f = v dd ) 02661-a - 002 scl t 4 t 2 t 1 t 3 t 5 t 6 sda data in sda data ou t fi g u r e 4 . i 2 c b u s ti ming d i ag r a m 02661-a - 004 200 ai oh 1.6v to output pin c l 50pf 200 ai ol f i gur e 5 . l o a d cir c ui t fo r a c c e ss t i me a n d bus reli nqui sh t i m e 02661-a - 005 4.7k ? 4.7k ? v dd to dac output 200pf f i gure 6. l o ad cir c uit for d a c o u tput s 02661-a - 003 t 1 t 2 t 3 t 5 t 6 t 4 t 7 t 8 d7 cs sclk din dout d 6 d 5 d 4 d 3 d 2 d 1 d 0 x x xxxxx x x x x x x x x x d 7 d 6d 5d 4 d 3 d 2 d 1 d 0 f i gure 7. s p i bus t i ming d i agr a m
adt7316/adt7317/adt7318 r e v. a | pa ge 7 o f 4 0 functional block diagram v dd value register external temperature value register a-to-d converter internal temperature value register on-chip temperature sensor analog mux d i g i t a l m u x limit comparator d i g i t a l m u x dac a registers dac b registers dac c registers dac d registers gain select logic power- down logic d+ d? smbus/spi interface cs scl/sclk sda/din dout/add int/int status registers v dd sensor v dd gnd internal reference v ref ?a b v ref ?c d ldac 7 8 6 5 4 13 12 11 9 3 14 10 v out ?d 15 v out ?c 16 v out ?b 1 v out ?a 2 string dac a string dac b string dac c string dac d ad t 7 3 1 6 / a d t 7317/ a d t 7318 address pointer register t high limit registers t low limit registers v dd limit registers control config. 1 register control config. 3 register control config. 2 register dac configuration register ldac configuration register interrupt mask registers 02661-a - 001 fi g u r e 8 .
adt7316/adt7317/adt7318 rev. a | page 8 of 40 dac ac characteristics table 2. guaranteed by design and characterization, but not production tested. v dd = 2.7 v to 5.5 v; r l = 4.7 k? to gnd; c l = 200 pf to gnd; 4.7 k? to v dd . all specifications t min to t max , unless otherwise noted. parameter 1 min typ (@ 25c) max unit conditions and comments output voltage settling time v ref = v dd = +5 v adt7318 6 8 s 1/4 scale to 3/4 scale change (0x40 to 0xc0). adt7317 7 9 s 1/4 scale to 3/ 4 scale change (0x100 to 0x300). adt7316 8 10 s 1/4 scale to 3/4 scale change (0x400 to 0xc00). slew rate 0.7 v/s major-code change glitch energy 12 nv-s 1 lsb change around major carry. digital feedthrough 0.5 digital crosstalk 1 nv-s analog crosstalk 0.5 nv-s dac-to-dac crosstalk 3 nv-s multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p. total harmonic distortion ?70 db v ref = 2.5 v 0.1 v p-p. frequency = 10 khz. 1 see section. terminology
adt7316/adt7317/adt7318 r e v. a | pa ge 9 o f 4 0 p a r a m e t e r r a t i n g absolute maximum ra tings table 3. v dd to gnd ?0.3 v to +7 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v digital output v o ltage to gnd ?0.3 v to v dd + 0.3 v reference input voltage to gnd ?0.3 v to v dd + 0.3 v operating tem p erature range ?40c to +120c storage temperature range ?65c to +150c junction tempe r ature 150c 16-lead qsop package power dissi pati on 1 (t j max ? t a )/ ja thermal imp e d a nce 2 ja junction-to- ambient 105.44c/w jc junction-to- case 38.8c/w ir reflow soldering peak temperature 220c (0/5c) time at peak te mperature 10 sec to 20 sec ramp-up rate 2c/sec to 3c/sec ramp-down rat e ?6c/sec 1 v a lue s r e la t e t o pa ck a g e bei n g u s e d o n a 4- la y e r boa r d . 2 junc tion-t o - c a s e r e s i s t anc e is ap pl icabl e t o c o mponen ts f e a t ur ing a pr ef e r en t i a l flo w di r e c t i o n , e . g . , c o m p o n en t s m o un t e d on a h e a t si n k . junc tion- t o - ambie n t res i s t anc e is mor e us eful f o r air- c ool ed p c b - moun t e d c o mpon en t s . s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . table 4. i 2 c a d d r ess selection add pin i 2 c addr ess low 1001 000 float 1001 010 high 1001 011 esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge without detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
adt7316/adt7317/adt7318 rev. a | page 10 of 40 pin conf igura t ion and fu nction descriptions 02661-a - 006 adt7316/ adt7317/ adt7318 top view (not to scale) v out -b 1 v out -c 16 v out -a 2 v out -d 15 v ref -ab 3 v ref -cd 14 cs 4 scl/sclk 13 gnd 5 sda/din 12 v dd 6 dout/add 11 d+ 7 int/int 10 d? 8 ldac 9 f i gure 9. pin config ur ation q s op table 5. adt7 316/adt73 17/adt7318 pin function descr i ptions pin no. mnemonic description 1 v ou t -b buffered analog output voltage from dac b. th e output amplifier has rai l -to-rail operation. 2 v ou t -a buffered analog output voltage from dac a. th e output amplifier has rai l -to-rail operation. 3 v ref -ab reference input pin for dacs a and b. it may be configured as a buffered or un buffered input to both dacs a and b. it has an input range from 0.25 v to v dd in unbuffe red mode and fr om 1 v to v dd in buffered mode. dacs a and b d e fault on pow er-up to this pin. 4 cs spi active low control input. this is the frame synchroni z ation signal fo r the input data. when cs goes lo w, it ena b les the input register and data is transferre d in on t h e rising ed ges and out on the falling ed ges of t h e subse q uent serial clocks. it is recommended that t h is pin be tied high to v dd when operating the serial interface in i 2 c mode. 5 gnd ground reference point for all circuitr y on the part. analog and digital ground . 6 v dd positive supply voltage, 2.7 v to 5.5 v. th e supply should be decoupled to ground. 7 d+ positive connection to ex ternal temperature sensor. 8 d? negative conne ction to ex ternal temperature sensor. 9 ldac active low control input that transfers the contents of the input registers to their respective da c registers. a falling edge on this pin forces any or al l dac registers to be upd a ted if the input registers have ne w d a ta. a minimum pulse width of 20 ns must be applied to the ldac pin to e n sure prope r lo ad ing of a dac register. t h is all o ws simultan eou s update of all dac outputs. bit c 3 of co ntrol con f iguration 3 register enabl e s ldac pin. default is with ldac pin controlling the loading of dac registers. 10 int/ int over limit interrupt. the output polar ity of this pin can be set to give an active low or active high interrupt when temperature or v dd limits are exceeded. default is active low. open-drain outputneeds a pull- up resistor. 11 dout/add spi, serial data output. logic output. data is clocked out of any register at this pin. data is clo c ked out on the falling ed ge of sclk. open-d r ain outp utneed s a pull-up resistor. add, i 2 c serial bus address selection pin. logic input. a low on this pin give s the address 1001 000, leaving it floating gives the address 1001 010 and setting it high gives the address 1001 011. the i 2 c address set up by the add pin is not latched by the device until after this address has been sent twice. on the eig h th scl cycle of the second valid communicatio n , the serial bus a d d r ess is latche d in. any subs equent changes on this pin will have no affect on the i 2 c serial bus ad d r ess. 12 sda/din sda, i 2 c serial data input. i 2 c ser i al data that is lo aded in to the devices register s is provided on this input. open- drain configuration need s a pull-up resistor. din, spi serial d a ta input. seri al data to be loaded into the devices register s is provided on this input. data is clocked into a register o n the rising ed ge of sclk. open - d r ain configura t ionneed s a p u ll-up resistor. 13 scl/sclk serial clock input. this is the clock input for the serial port. the serial c l oc k is used to clock data out of any re gister of the adt7316/a d t7317/adt73 18 and also to clock data into any register that c a n be written to. open-drain configuration need s a pull-up resistor. 14 v ref -cd reference input pin for dacs c and d. it may be configured as a buffered or un buffered input to both dacs c an d d. it has an input range from 0.25 v to v dd in unbuffe red mode and fr om 1 v to v dd in buffered mode. dacs c and d default on pow er-up, to this pin. 15 v ou t -d buffered analog output voltage from dac d. th e output amplifier has rai l -to-rail operation. 16 v ou t -c buffered analog output voltage from dac c. th e output amplifier has rai l -to-rail operation.
adt7316/adt7317/adt7318 rev. a | page 11 of 40 terminology relative accuracy relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. typical inl versus code plots can be seen in figure 10, figure 11, and figure 12. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 0.9 lsb maximum ensures monotonicity. typical dac dnl versus code plots can be seen in figure 13, figure 14, and figure 15. offset error this is a measure of the offset error of the dac and the output amplifier. (see figure 2 and figure 3.) it can be negative or positive. it is expressed as a percentage of the full-scale range. gain error this is a measure of the span error of the dac. it is the devi- ation in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in ppm of full-scale range/c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in ppm of full-scale range/c. long term temperature drift this is a measure of the change in temperature error with the passage of time. it is expressed in degrees celsius. the concept of long term stability has been used for many years to describe by what amount an ics parameter would shift during its life- time. this is a concept that has been typically applied to both voltage references and monolithic temperature sensors. unfor- tunately, integrated circuits cannot be evaluated at room tem- perature (25c) for 10 years or so to determine this shift. as a result, manufacturers very typically perform accelerated lifetime testing of integrated circuits by operating ics at elevated temperatures (between 125c and 150c) over a shorter period of time (typically between 500 and 1000 hours). as a result of this operation, the lifetime of an integrated circuit is signifi- cantly accelerated due to the increase in rates of reaction within the semiconductor material. dc power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in decibels. v ref is held at 2 v and v dd is varied 10%. dc crosstalk this is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac while monitoring another dac. it is expressed in v. reference feedthrough this is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated (i.e., ldac is high). it is expressed in decibels. channel-to-channel isolation this is the ratio of the amplitude of the signal at the output of one dac to a sine wave on the reference input of another dac. it is measured in decibels. major-code transition glitch energy major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital code is changed by 1 lsb at the major carry transition (01111 to 10000 or 100...00 to 01111). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of a dac from the digital input pins of the device but is measured when the dac is not being written to. it is specified in nv-s and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s or vice versa. digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv-s. analog crosstalk this is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping ldac high. pulse ldac low and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv-s.
adt7316/adt7317/adt7318 rev. a | page 12 of 40 dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with ldac low and monitoring the output of another dac. the energy of the glitch is expressed in nv-s. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion this is the difference between an ideal sine wave and its atten- uated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measure of the harmonics present on the dac output. it is measured in decibels. round robin this term is used to describe the adt7316/adt7317/ adt7318 cycling through the available measurement channels in sequence, taking a measurement on each channel. dac output settling time this is the time required, following a prescribed data change, for the output of a dac to reach and remain within 0.5 lsb of the final value. a typical prescribed change is from 1/4 scale to 3/4 scale.
adt7316/adt7317/adt7318 rev. a | page 13 of 40 typical perf orm ance cha r acte ristics 0.20 0 5 0 100 150 dac code inl e r ror (ls b ) 200 250 02661-a - 009 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 f i gur e 1 0 . ad t7 31 8 t y pi c a l inl p l o t 0.6 0 200 400 600 dac code inl e rror (ls b ) 800 1000 ?0.6 ?0.4 ?0.2 0 0.2 0.4 02661-a - 010 f i gur e 1 1 . ad t7 31 7 t y pi c a l inl p l o t 2.5 0 500 1000 1500 2000 2500 3000 3500 4000 dac code inl e rror (ls b ) ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 02661-a - 011 f i gur e 1 2 . ad t7 31 6 t y pi c a l inl p l o t 0.10 0 5 0 100 150 200 250 dac code dnl e rror (ls b ) ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 02661-a - 012 f i gur e 1 3 . ad t7 31 8 t y pi c a l dnl p l o t 0.3 0 200 400 600 800 1000 dac code dnl e rror (ls b ) ?0.3 ?0.2 ?0.1 0 0.1 0.2 02661-a - 013 f i gur e 1 4 . ad t7 31 7 t y pi c a l dnl p l o t 1.0 0 500 1000 1500 2000 2500 3000 3500 4000 dac code dnl e rror (ls b ) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 02661-a - 014 f i gur e 1 5 . ad t7 31 6 t y pi c a l dnl p l o t
adt7316/adt7317/adt7318 rev. a | page 14 of 40 0.30 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v ref (v) e rror (ls b ) ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 inl wcp dnl wcp dnl wcn inl wcn 02661-a - 015 f i gure 16. a d t 7 3 1 8 inl e rror and dnl e r r o r v s . v ref 0.14 ?40 110 80 50 20 ?10 temperature ( c) e rror (ls b ) ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 0.12 dnl wcn inl wcp dnl wcp inl wcn 02661-a - 016 f i gure 17. a d t 7 3 1 8 inl e rror and dnl e r r o r v s . t e mpe r atu r e 0 ?40 120 100 80 60 40 20 0 ?20 temperature ( c) e rror (ls b ) ?1.8 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 offset error gain error 02661-a - 017 f i gure 18. o ffs et e r r o r a n d g a in e rror v s . t e mpe r atu r e e rror (ls b ) ?20 ?15 ?10 ?5 0 5 10 2.7 3.3 3.6 4.0 v dd (v) 4.5 5.0 5.5 offset error gain error v ref = 2.25v 02661-a - 018 f i gure 19. o ffs et e r r o r a n d g a in e rror v s . v dd source current sink current 2.505 dac outp ut (v ) 2.465 2.470 2.475 2.480 2.485 2.490 2.495 2.500 01 2 3 current (ma) 45 6 v dd =5 v v re f =5 v dac outp ut loade d t o m ids cale 02661-a - 019 f i g u re 20. v ou t s o u r c e and sink curr ent c a pab i lit y 1.98 0 4000 3500 3000 2500 2000 1500 1000 500 dac code i cc (ma) 1.86 1.88 1.90 1.92 1.94 1.96 dac output unloaded dac output loaded 02661-a - 020 f i gure 21. sup p l y current v s . d a c cod e
adt7316/adt7317/adt7318 rev. a | page 15 of 40 2.00 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 v cc (v) i cc (ma) 1.75 1.80 1.85 1.90 1.95 adc off, dac outputs at 0v 02661-a - 021 f i gure 22. sup p l y current v s . sup p ly v o ltag e @ 2 5 c 7 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 v cc (v) i cc ( a) 0 1 2 3 4 5 6 02661-a - 022 f i gure 23. p o wer - d o wn cur r ent vs. su p p ly v o ltage @ 25 c 4.0 02 4 6 8 1 time ( s) dac outp ut (v ) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 02661-a - 023 f i g u re 24. h a lf -s c a l e s e t t ling ( 1 / 4 t o 3/ 4 s c a l e cod e ch an g e ) 1.8 dac outp ut (v ) 0.8 1.0 1.2 1.4 1.6 0.6 02 4 time ( s) 68 0.4 0.2 0 1 0 02661-a - 024 f i g u re 25. e x it ing p o wer - d o wn to m i d s c a l e 0.4700 02 4 6 8 1 time ( s) dac outp ut (v ) 0.4650 0.4655 0.4660 0.4665 0.4670 0.4675 0.4680 0.4685 0.4690 0.4695 0 02661-a - 025 f i gur e 2 6 . ad t7 31 6 ma jo r - c o de t r a n s i ti o n gl it c h ene r gy0 .11 to 10 0 00 0.4730 02 46 8 1 time ( s) dac outp ut (v ) 0.4685 0.4690 0.4695 0.4700 0.4705 0.4710 0.4715 0.4720 0.4725 0 02661-a - 026 f i g u re 27. a d t 7 3 1 6 m a j o r - code t r ans i t i on g l i t ch e n er g y 1 00 0 0 to 01 1 11
adt7316/adt7317/adt7318 rev. a | page 16 of 40 0 full-s cale e rror (mv ) ?12 ?10 ?8 ?6 ?4 ?2 12 3 v ref (v) 45 v dd =5 v t a =2 5 c 02661-a - 027 f i gure 28. f u ll- s c al e e rror v s . v ref 2.329 01 2 3 4 5 time ( s) dac outp ut (v ) 2.322 2.323 2.324 2.325 2.326 2.327 2.328 v dd = 5v v ref = 5v dac output loaded to midscale 02661-a - 028 f i gure 29. d a c-to -d a c crosstalk ?1 0 ac p s rr (db) ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 0 1 1 0 100 02661-a - 029 frequency (khz) 100mv ripple on v cc v ref = 2.25v v dd = 3.3v temperature = 25 c f i g u r e 3 0 . p s r r v s . s u pp l y r i pp le f r e q u e n c y 1.5 te mp e rature e rror ( c) ? 1.0 ? 0.5 0 0.5 1.0 ?3 0 0 40 temperature ( c) 85 120 inte rn al te mp era t u r e @ 3.3 v int e rn al te mp er a t u r e @ 5v exte r n a l tem per a t u r e @ 5 v ex te rnal te mp e r a t ure @ 3 .3v 02661-a - 030 f i g u re 31. t e mpe r a t ur e e r r o r @ 3. 3 v a n d 5 v 15 te mp e rature e rror ( c) ?10 ?5 0 5 10 ?15 ?20 ?25 01 0 2 0 pcb track resistance (m ? ) 30 40 50 60 70 80 90 100 02661-a - 031 d+ to v cc d+ to gnd v dd =3 . 3 v te mp era t ure = 2 5 c f i g u re 32. e x ter n a l t e m p er at ure e r r o r v s . pcb t r ack r e s i s t anc e 0 5 10 15 20 25 capacitance (nf) te mp e rature e rror ( c) ?60 ?50 ?40 ?30 ?20 ?10 0 30 35 40 45 50 v dd =3 . 3 v 02661-a - 032 f i gure 33. e x ter n a l t e m p er ature e r r o r v s . capacit a nce be t w een d+ and d ?
adt7316/adt7317/adt7318 rev. a | page 17 of 40 10 te mp e rature e r ror ( c) 0 2 4 6 8 ?2 ?4 ?6 1 100 200 noise frequency (hz) 300 400 500 600 v dd = 3.3v common-mode voltage = 100mv 02661-a - 033 f i gure 34. e x ter n a l t e m p er ature e r r o r v s . com m on-m ode no ise f r equ e nc y 70 te mp e rature e r ror ( c) 20 30 40 50 60 10 0 ?10 1 100 200 noise frequency (mhz) 300 400 500 600 v dd = 3.3v differential-mode voltage = 100mv 02661-a - 034 f i gure 35. e x ter n a l t e m p er ature e r r o r v s . d i ffer e nti a l-m o de n o ise f r equenc y 0.6 te mp e rature e rror ( c) ? 0.4 ? 0.2 0 0.2 0.4 ? 0.6 1 100 200 noise frequency (hz) 300 400 500 600 250mv v dd = 3.3v 02661-a - 035 f i gure 36. inte rn al t e m p er ature e r r o r v s . p o wer sup p l y n o is e f r equenc y 140 te mp e rature ( c) 40 60 80 100 120 20 01 0 2 0 time (s) 30 40 50 0 60 02661-a - 036 internal temperature external temperature t e m p e r a t u r e o f e n v i r o n m e n t c h a n g e d h e r e f i gur e 3 7 . t e m p er atur e se nsor re spo n se t o ther ma l sho c k 0 atte nuation (db) ?25 ?20 ?15 ?10 ?5 1 10 100 1k 10k 100k 1m 10m 02661-a - 037 frequency (hz) f i gure 38. multip lying band width (sma ll -si g na l f r e q uenc y re sp o n se )
adt7316/adt7317/adt7318 rev. a | page 18 of 40 theory of operation directly after the power-up calibration routine, the adt7316/ adt7317/adt7318 go into idle mode. in this mode, the device is not performing any measurements and is fully powered up. all four dac outputs are at 0 v. to begin monitoring, write to control configuration 1 register (address = 18h), and set bit c0 = 1. the adt7316/adt7317/ adt7318 go into their power-up default measurement mode, which is round robin. the device proceeds to take measure- ments on the v dd channel, the internal temperature sensor channel, and the external temperature sensor channel. once it finishes taking measurements on the external temperature sensor channel, the device immediately loops back to start taking measurements on the v dd channel and repeats the same cycle as before. this loop continues until the monitoring is stopped by resetting bit c0 of control configuration 1 register to 0. it is also possible to continue monitoring as well as switching to single-channel mode by writing to control configuration 2 register (address = 19h) and setting bit c4 = 1. further expla- nation of the single-channel and round robin measurement modes are given in later sections. all measurement channels have averaging enabled on power-up. averaging forces the device to take an average of 16 readings before giving a final measured result. to disable averaging and consequently decrease the conversion time by a factor of 16, set c5 = 1 in control configuration 2 register. controlling the dac outputs can be done by writing to the dacs msb and lsb registers (addresses 10h to 17h). the power-up default setting is to have a low going pulse on the ldac pin controlling the updating of the dac outputs from the dac registers. alternatively, users can configure the updating of the dac outputs to be controlled by means other than the ldac pin by setting c3 = 1 of the control confi- guration 3 register (address = 1ah). the dac configuration register (address = 1bh), and the ldac configuration register (address = 1ch) can now be used to control the dac updating. these two registers also control the output range of the dacs, enabling or disabling the external reference buffer, and selecting between the internal or external reference. dac a and dac b outputs can be configured to give a voltage output proportional to the temperature of the internal and external temperature sensors, respectively. the dual-serial interface defaults to the i 2 c protocol on power- up. to select and lock in the spi protocol, follow the selection process as described in the serial interface selection section. the i 2 c protocol cannot be locked in, while the spi protocol, when selected, is automatically locked in. the interface can only be switched back to be i 2 c when the device is powered off and on. when using i 2 c, the cs pin should be tied to either v dd or gnd. there are a number of different operating modes on the adt7316/adt7317/adt7318 devices, and all of them can be controlled by the configuration registers. these features consist of enabling and disabling interrupts, polarity of the int/ int pin, enabling and disabling the averaging on the measurement channels, smbus timeout, and software reset. power-up calibration it is recommended that no communication to the part is ini- tiated until approximately 5 ms after v dd has settled to within 10% of its final value. it is generally accepted that most systems take a maximum of 50 ms to power-up. power-up time is directly related to the amount of decoupling on the voltage supply line. during this 5 ms after v dd has settled, the part is performing a calibration routine, and any communication to the device will interrupt this routine and could cause erroneous temperature measurements. if it is not possible to have v dd at its nominal value by the time 50 ms has elapsed, or that communication to the device has started prior to v dd settling, then it is recom- mended that a measurement be taken on the v dd channel before a temperature measurement is taken. the v dd measure- ment is used to calibrate out any temperature measurement error due to different supply voltage values. conversion speed the internal oscillator circuit used by the adc has the capa- bility to output two different clock frequencies. this means that the adc is capable of running at two different speeds when performing a conversion on a measurement channel. thus the time taken to perform a conversion on a channel can be reduced by setting c0 of control configuration 3 register (address 1ah). this increases the adc clock speed from 1.4 khz to 22 khz. at the higher clock speed, the analog filters on the d+ and d? input pins (external temperature sensor) are switched off. this is why the power-up default setting is to have the adc working at the slow speed. the typical times for fast and slow adc speeds are given in the specification pages. the adt7316/adt7317/adt7318 power up with averaging on. this means every channel is measured 16 times and inter- nally averaged to reduce noise. the conversion time can also be sped up by turning the averaging off by setting bit c5 of con- trol configuration 2 register (address = 19h) to a 1.
adt7316/adt7317/adt7318 rev. a | page 19 of 40 functional description vol t a ge output digit a l - t o -anal o g c o nverters the adt7316 /adt7317/ad t7318 ha v e f o ur r e sis t o r -s tr in g d a c s f a br i c a t e d on a c m o s pro c e s s , w i t h re s o lut i ons of 1 2 , 1 0 , a nd 8 b i ts, r e sp e c t i vely . t h e y con t a i n fo ur o u t p u t b u f f er a m pli- f i e r s , and are w r i tte n to v i a a n i 2 c se rial in t e rf a c e o r a n s p i se ri al i n t e rf a c e . see th e se r i al i n t e rf a c e s e l e cti o n secti o n f o r more i n for m a t i o n . the adt7316 /adt7317/ad t7318 o p era t e f r o m a sing le s u p - p l y o f 2.7 v t o 5 . 5 v , an d t h e o u t p u t b u f f er a m p l if iers p r o v ide ra il-t o-ra il o u t p u t swin g wi th a s l ew r a t e o f 0.7 v/s. d a cs a a nd b s h a r e a c o mm on ext e r n a l r e fer e n c e i n p u t, nam e l y v ref -ab . d a cs c a nd d s h a r e a co mm on ext e r n al r e fer e n c e in p u t, name ly v ref - c d . e a c h re f e re nc e i n p u t m a y b e bu f f e r e d to dra w v i r t ual l y no c u r r en t f r o m t h e r e fer e n c e s o ur ce o r un b u f - f e re d to g i ve a re f e re nc e i n put r a nge f r om g n d to v dd . th e de vices h a ve a p o w e r - do w n m o de i n w h ich a l l d a cs m a y b e tu r n e d of f c o mp l e t e l y w i t h a h i g h i m p e d a nc e o u tpu t . e a c h d a c o u t p u t wil l n o t b e u p da t e d u n til i t r e cei v es t h e ld a c co mmand . th er efo r e , w h i l e t h e d a c r e g i s t ers w o u l d ha v e b e e n wr i t ten t o wi t h a ne w va l u e , t h is va lue wi l l n o t b e r e p r es en t e d b y a v o l t a g e o u t p u t un t i l t h e d a cs ha v e r e cei v e d t h e ld a c co mma n d . re ading b a ck f r o m an y d a c r e g i s t er p r ior to issu ing an l d a c c o m m and wi l l re su lt in t h e d i g i t a l val u e t h a t co r r es p o n d s t o t h e d a c o u t p ut v o l t ag e . th er efo r e , t h e dig i t a l val u e wr i t t e n t o t h e d a c r e g i s t er cann ot b e r e ad ba c k un til a f t e r th e l d a c co mm a n d h a s been i n i t ia t e d . th i s ld a c co m m and can b e g i ve n b y ei t h er p u l l in g t h e ld a c pi n lo w (fal ling e d ge lo ads d a cs), s e t t in g u p bi ts d4 a nd d5 o f d a c c o nf igur a t io n r e g i ster (a ddr ess = 1bh), o r usin g t h e ld a c r e g i st er (a ddr es s = 1c h). whe n u s i n g t h e ld a c pi n to c o n t ro l d a c re g i st e r l o a d i n g , t h e lo w g o in g p u ls e wid t h sh o u ld be 20 n s minim u m. th e ld a c p i n has to go hig h an d lo w a g ai n b e fo r e t h e d a c r e g i sters can be r e loa d ed . 02661-a - 038 buffer select signal v ref -ab int v ref reference buffer gain mode (gain = 1 or 2) v out -a output buffer amplifier dac register input register resistor string f i gure 39. sing le da c chann e l a r ch itectur e digit a l - t o -anal o g se c t ion t h e arch ite c tu r e of a d a c ch a n n e l c o ns i s t s of a re s i stor st r i ng d a c fol l o w e d b y a n o u t p u t b u f f er a m plif ier . the v o l t a g e a t t h e v ref pi n or t h e on - c h i p re f e re n c e of 2 . 2 8 v pro v i d e s t h e re f e r - en c e v o l t a g e fo r t h e co r r es p o ndin g d a c. f i gure 39 sh o w s a bl o c k d i ag r a m of t h e d a c arch ite c t u re. s i nc e t h e i n put c o d i ng t o t h e d a c is st ra ig h t b i na r y , t h e ide a l o u t p u t vol t a g e is g i v e n by n ref out d v v 2 = w h er e: d = t h e de cim a l e q ui va le n t o f t h e b i na r y co de t h a t is lo ade d to th e d a c r e gis t er : 0C255 f o r ad t7318 (8 b i ts) 0C1023 f o r ad t7317 (10 b i ts) 0C4095 f o r ad t7316 (12 b i ts) n = th e d a c r e so l u ti o n resist or string the r e sist o r st r i n g s e c t ion is sho w n i n f i gur e 4 0 . i t is sim p ly a s t r i n g o f r e sis t o r s, eac h o f val u e 603 ? a p p r o x ima t e l y . th e dig i t a l co de lo a d e d to t h e d a c r e g i ster deter m in es a t w h a t n o de o n t h e s t r i n g t h e v o l t a g e is t a p p e d o f f t o b e fe d in t o t h e o u t p ut a m pl if ier . the v o l t a g e is t a p p e d o f f b y closin g o n e o f t h e swi t ch es co nn e c t i n g t h e s t r i n g to t h e am plif ier . b e ca us e i t is a st r i ng of re s i stors , i t is g u ar an te e d monotonic . r r r r r to output amplifier 02661-a - 039 f i gur e 4 0 . resi st or str i ng d a c exter n al reference input s ther e is a r e fer e n c e pin fo r e a ch p a ir o f d a cs. the r e fer e n c e in p u ts a r e b u f f er e d , b u t can a l s o b e i ndivi d u a l ly co nf igur e d as un b u f f er ed . the adva n t a g e wi t h t h e b u f f er e d in p u t is t h e hi g h im p e dan c e i t p r es en ts t o t h e v o l t a g e s o ur ce dr i v i n g i t . h o we ver , if t h e u n b u f - fer e d m o de is us e d , t h e us er can ha ve a r e fer e nce v o l t a g e as lo w as 0.25 v a nd as hig h as v dd , sin c e t h er e is n o res t r i c t io n d u e to he a d ro om a n d f o ot ro om of t h e re f e re nc e am pl i f i e r .
adt7316/adt7317/adt7318 rev. a | page 20 of 40 i f t h er e is a b u f f er e d r e fer e n c e i n t h e cir c u i t, t h er e is n o n e e d to us e t h e o n -chi p b u f f ers. i n u n b u f f er e d m o de , t h e in pu t i m p e - dan c e is s t i l l l a rg e a t typ i cal l y 9 0 k? p e r r e fer e n c e in p u t fo r 0 v to v ref o u t p u t m o de and 45 k? f o r 0 v t o 2 v ref output mo d e . the b u f f er e d /u n b uf fer e d o p t i on is co n t r o l l e d b y t h e d a c c o nf igura t ion r e g i s t er (a ddr e s s 1bh, s e e r e g i s t ers s e c t io n). the ld a c c o nf igura t io n r e g i st er con t r o ls t h e o p t i o n t o s e le c t b e tw e e n i n t e r n a l a nd ext e r n al vol t a g e r e fer e n c e s . th e de fa u l t s e t t in g is fo r ext e r n a l r e fer e n c e s e le c t e d . 02661-a - 040 string dac a string dac b v ref -ab 2.25v internal v ref f i gure 41. d a c r e f e r e nc e buffer c i rcui t outpu t am plifier the o u t p u t b u f f er a m plif ier is c a p a b l e o f ge n e ra t i n g o u t p u t v o l t a g es t o wi t h in 1 mv o f ei t h e r ra i l . i t s ac t u al ra n g e dep e nds o n t h e va l u e o f v ref , ga in an d of fs et er r o r . i f a ga in o f 1 is s e lec t e d (b i t s 0C3 o f d a c c o nf igura t io n r e g i st er = 0), th e o u t p u t ra n g e is 0.001 v t o v ref . i f a ga in o f 2 is s e lec t e d (b i t s 0C3 o f d a c c o nf igura t io n r e g i st er = 1), th e o u t p u t ra n g e is 0.001 v t o 2v ref . b e ca u s e o f c l am p i ng, h o we ver , t h e m a x i m u m o u t p u t is limi te d to v dd C 0.001 v . the o u t p u t am plif ier is ca p a b l e o f dr i v i n g a lo a d o f 4.7 k? t o v dd o r 4.7 k? t o gnd in p a ral l e l wi t h 200 pf to gnd (s ee f i gur e 6). th e s o ur ce a nd sin k ca p a b i li t i es o f t h e o u t p ut a m plif ier can b e s e en i n t h e plo t in f i gur e 20. the s l e w ra t e is 0.7 v/s wi th a half-s c a le s e t t lin g tim e t o 0.5 ls b (a t 8 b i ts) o f 6 s. thermal vol t a g e output the adt7316 /adt7317/ad t7318 a r e ca p a b l e o f o u t p u t tin g vo lt age s t h at are prop or t i on a l to te m p e r atu r e. d a c a output ca n b e co nf igure d t o r e p r es en t t h e t e m p era t ur e o f t h e i n t e r n al s e n s o r w h i l e d a c b o u t p ut can b e co nf igur e d t o r e p r es en t t h e ex ter n a l te m p er a t ur e s e n s o r . bi t s c5 a nd c6 o f c o n t r o l c o nf ig - ura t io n 3 r e g i ster s e le c t t h e t e m p era t ur e p r o p o r t i o n al t o o u t p u t v o l t a g e . e a ch t i m e a t e m p er a t u r e m e as ur emen t is t a k e n t h e d a c ou tput i s up d a t e d. t h e o u tpu t re s o lut i on f o r t h e a d t 7 3 1 8 is 8 b i ts w i t h t h e 1c cha n g e cor r es p o n d in g t o t h e on e ls b c h a n g e . th e ou t p u t r e s o l u tio n fo r th e ad t731 6 a nd adt7317 is ca p a b l e o f 10 b i ts wi t h a 0.25c c h a n g e co r r es p o ndin g t o t h e 1 ls b c h a n g e 02661- a- 041 c1 d+ low-pass filter f c = 65khz bias diode v dd to adc v out+ v out ? remote sensing transistor (2n3906) optional capacitor, up to 3nf max. can be added to improve high frequency noise rejection in noisy environments d? i n i i bias f i g u re 42. sig n al condit ion i ng f o r e x t e rn al d i ode t e mpe r at ure s e ns o r s the def a u l t o u t p u t r e s o l u tio n fo r th e ad t731 6 a nd adt7317 is 8 b i ts. t o in cr eas e this t o 10 b i ts , s e t c1 = 1 o f c o n t r o l c o nf ig- ura t io n 3 r e g i ster . the def a u l t ou t p ut ra n g e is 0 v t o v ref -ab , a nd t h is c a n b e in cr e a s e d to 0 v to 2 v ref -ab . the us er can se l e ct th e in t e rnal v ref (v ref = 2 . 28 v) b y s e t t ing d4 = 1 in t h e ld a c c o nf igur a t io n r e g i ster (a ddr ess 1c h). i n cr e a sing t h e out p ut volt age s p an to 2 v ref can b e don e b y s e tt in g d0 = 1 fo r d a c a (in t er na l t e m p era t ur e s e n s o r ), a nd d1 = 1 fo r d a c b (ex t er na l tem p e r a t ur e s e n s o r ) i n d a c c o nf igu r a t io n r e g i ster (a ddr ess 1bh). the o u t p u t v o l t a g e is c a p a b l e o f t r ackin g a maxim u m t e m p er - a t ur e ra n g e o f ? 128c t o +127c, b u t t h e defa u l t s e t t in g is ?40c t o +127c. i f t h e o u t p u t v o l t a g e ra n g e is 0 v t o v ref -ab (v ref -ab = 2.25 v), t h en this cor r es p o n d s t o 0 v r e p r es en t i n g ?40c, a nd 1.48 v r e p r es en tin g +127c. this o f co urs e wil l g i v e a n u p p e r de a d b a nd b e t w e e n 1 . 48 v a nd v ref -a b . the i n t e r n al and ext e r n al a n alo g t e m p era t ur e o f fs et r e g i s t ers ca n b e us e d to v a r y t h is u p p e r de ad b a nd an d c o n s e q ue n t ly t h e t e m p era t ur e t h a t 0 v co r r es p o nds t o . t a b l e 6 a nd t a b l e 7 g i v e exa m ples o f h o w t h is is don e u s in g a d a c o u t p u t v o l t a g e sp an of v ref a nd 2 v re f , r e s p e c t i v e l y . sim p l y wr i t e in t h e t e m p era t ur e val u e , in tw os c o m p lemen t f o r m a t , a t w h ich 0 v is t o s t a r t. f o r exa m ple , if using t h e d a c a o u t p u t w i t h 0 v t o st a r t a t ? 40c, p r og ra m d8h i n t o t h e i n t e r n al a n alog t e m p era t ur e o f fs et r e g i s- t e r (a ddr es s 21 h). this is an 8-b i t r e g i s t er an d th us o n l y has a t e m p era t ur e o f fs et r e s o l u t i on o f 1c fo r al l de v i ce mo de ls. u s e t h e fol l o w in g fo r m u l as t o det e r m i n e t h e val u e to p r og ra m in t o t h e o f fs et r e g i sters. ne g a t i v e t e m p e r a t u r e s : ( ) ( ) 128 0 + = temp v d code register offset w h er e: d7 o f of fs et re g i s t er c o de is s e t t o 1 fo r n e ga t i v e t e m p era t ur es . exa m p l e : ( ) ( ) 58h d 88 128 40 = = + ? = d code register offset since a nega t i ve t e m p era t ur e has b e e n i n p u t in to t h e e q u a t i o n , d b 7 (ms b ) o f t h e of fs et reg i s ter c o de is s et t o a 1 . th er efo r e , 58h be co m e s d8h. ( ) h d db h 8 1 7 58 = +
adt7316/adt7317/adt7318 rev. a | page 21 of 21 positive temperatures: () temp v d code register offset 0 = example: () ah d d code register offset 0 10 = = the following equation is used to work out the various temperatures for the corresponding 8-bit dac output: ( ) ( ) temp v lsb p o dac temp bit 0 1 / 8 + = ? for example, if the output is 1.5 v, v ref -ab = 2.25 v, 8-bit dac has an lsb size = 2.25 v/256 = 8.79 10 C3 , and 0 v temp is at ?128c, then the resultant temperature is () () c o 43 128 10 79 . 8 5 . 1 3 + = ? + ? the following equation is used to work out the various temperatures for the corresponding 10-bit dac output ( ) ( ) ( ) temp v lsb p o dac temp bit 0 25 . 0 1 / 10 + = ? for example, if the output is 0.4991 v, v ref -ab = 2.25 v, 10-bit dac has an lsb size = 2.25 v/1024 = 2.197 10-3, and 0 v temp is at ?40c, then the resultant temperature works out to be () () () c o 75 . 16 40 25 . 0 10 197 . 2 4991 . 0 3 + ? + ? table 6. thermal voltage output (0 v to v ref -ab) o/p voltage (v) default (c) max (c) sample (c) 0 ?40 ?128 0 0.5 +17 ?71 +56 1 +73 ?15 +113 1.12 +87 ?1 +127 1.47 +127 +39 udb 1 1.5 udb 1 +42 udb 1 2 udb 1 +99 udb 1 2.25 udb 1 +127 udb 1 table 7. thermal voltage output (0 v to 2 v ref -ab) o/p voltage (v) default (c) max (c) sample (c) 0 ?40 ?128 0 0.25 ?26 ?114 +14 0.5 +12 ?100 +28 0.75 +3 ?85 +43 1 +17 ?71 +57 1.12 +23 ?65 +63 1.47 +43 ?45 +83 1.5 +45 ?43 +85 2 +73 ?15 +113 2.25 +88 0 +127 2.5 +102 +14 udb 1 2.75 +116 +28 udb 1 3 udb 1 +42 udb 1 3.25 udb 1 +56 udb 1 3.5 udb 1 +70 udb 1 3.75 udb 1 +85 udb 1 4 udb 1 +99 udb 1 4.25 udb 1 +113 udb 1 4.5 udb 1 +127 udb 1 figure 43 shows dac output versus temperature for a v ref -ab= 2.25 v. temperature ( c) dac output (v) 0 0.15 ?128?110 ?90 ?70 ?50 ?30 ?10 10 30 50 70 90 110 127 02661-a-042 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 1.65 1.80 1.95 2.10 2.25 0v = ?128 c 0v = ?40 c 0v = 0 c figure 43. 10-dac output vs. temperature, v ref -ab = 2.25 v 1 upper dead band has been reached. dac output is not capable of increasing (see figure 3).
adt7316/adt7317/adt7318 rev. a | page 22 of 40 functional descriptionmeasurement temperature sensor the adt7316/adt7317/adt7318 contain an adc with special input signal conditioning to enable operation with external and on-chip diode temperature sensors. when the adt7316/adt7317/adt7318 are oper ating in single-channel mode, the adc continually processes the measurement taken on one channel only. this channel is preselected by bits c0 and c1 in control configuration 2 register (address 19h). when in round robin mode, the analog input multiplexer sequentially selects the v dd input channel, the on-chip temperature sensor to measure its internal temperature, and the external temperature sensor. these signals are digitized by the adc and the results stored in the various value registers. the measured results are compared with the internal and external, t high and t low , limits. these temperature limits are stored in on-chip registers. if the temperature limits are not masked out, any out-of-limit comparisons generate flags that are stored in the interrupt status 1 register. one or more out-of- limit results will cause the int/ int output to pull either high or low depending on the output polarity setting. theoretically, the temperature measuring circuit can measure temperatures from ?128c to +127c with a resolution of 0.25c. temperatures outside t a , however, are outside the guar- anteed operating temperature range of the device. temperature measurement from ?128c to +127c is possible using an external sensor. temperature measurement is initiated by three methods. the first method is applicable when the part is in single-channel measurement mode. the temperature is measured 16 times and internally averaged to reduce noise. in single-channel mode, the part is continuously monitoring the selected channel, i.e., as soon as one measurement is taken then another one is started on the same channel. the total time to measure a temperature channel with the adc operating at slow speed is typically 11.4 ms (712 s 16) for the internal temperature sensor, and 24.22 ms (1.51 ms 16) for the external temperature sensor. the new temperature value is stored in two 8-bit registers and ready for reading by the i 2 c or spi interface. the user has the option of disabling the averaging by setting a bit (bit 5) in the control configuration 2 register (address 19h). the adt7316/ adt7317/adt7318 default on power-up, with the averaging enabled. the second method is applicable when the part is in round robin measurement mode. the part measures both the internal and external temperature sensors as it cycles through all possi- ble measurement channels. the two temperature channels are measured each time the part runs a round robin sequence. in round robin mode, the part is continuously measuring all channels. temperature measurement is also initiated after every read or write to the part when the part is in either single-channel measurement mode or round robin measurement mode. once serial communication has started, any conversion in progress is stopped and the adc reset. conversion will start again imme- diately after the serial communication has finished. the temp- erature measurement proceeds normally as described above. v dd monitoring the adt7316/adt7317/adt7318 also have the capability of monitoring their own power supplies. the parts measure the voltage on their v dd pin to a resolution of 10 bits. the resultant value is stored in two 8-bit registers, the 2 lsbs stored in register address 03h and the 8 msbs are stored in register address 06h. this allows the user to have the option of just doing a one byte read if 10-bit resolution is not important. the measured result is compared with v high and v low limits. if the v dd interrupt is not masked out, any out-of-limit comparison generates a flag in interrupt status 2 register and one or more out-of-limit results will cause the int/ int output to pull either high or low depending on the output polarity setting. measuring the voltage on the v dd pin is regarded as monitoring a channel. therefore, along with the internal and external temperature sensors, the v dd voltage makes up the third and final monitoring channel. the user can select the v dd channel for single-channel measurement by setting bit c4 = 1 and setting bits c0 to c2 to all 0s in control configuration 2 register. when measuring the v dd value, the reference for the adc is sourced from the internal reference. table 8 shows the data format. as the maximum v dd voltage measurable is 7 v, internal scaling is performed on the v dd voltage to match the 2.28 v internal reference value. below is an example of how the transfer function works. v dd = 5 v adc reference = 2.28 v 1 lsb = adc reference/ 2 10 = 2.28/1024 = 2.226 mv scale factor = full-scale v cc /adc reference = 7/2.28 = 3.07 conversion result = v dd /( scale factor lsb size ) = 5/(3.07 2.226 mv ) = 2dbh
adt7316/adt7317/adt7318 rev. a | page 23 of 40 table 8. v dd data form at, v re f = 2. 28 v digital output v dd val u e ( v ) b i nary hex 2.5 01 0110 1110 16e 3.0 01 1011 0111 1b7 3.5 10 0000 0000 200 4.0 10 0100 1001 249 4.5 10 1001 0010 292 5.0 10 1101 1100 2dc 5.5 11 0010 0101 325 6.0 11 0110 1110 36e 6.5 11 1011 0111 3b7 7.0 11 1111 1111 3ff on- c hip reference the adt7316 /adt7317/ad t7318 has a n o n -c hi p 1.2 v band ga p r e f e r e n c e tha t is ga in e d u p b y a s w i t ch ed ca p a ci t o r a m p l if ier t o g i v e a n o u t p u t o f 2.28 v . th e a m p l if ier is p o wer e d u p f o r th e d u r a t i on o f t h e de vice m o ni to r i n g phas e and is p o w e r e d do wn o n ce m o n i to r i ng is dis a b l e d . t h is s a ves o n c u r r en t co nsum p - t i on . t h e i n te r n a l re f e re nc e i s u s e d a s t h e re f e re nc e f o r t h e ad c. the ad c is us e d fo r me as ur in g v dd a nd t h e i n ter n a l and ext e r n al t e m p er a t ur e s e n s o r s. th e in t e r n al r e fer e n c e is alw a ys used w h en m e as uri n g v dd , a n d t h e in t e r n al and ext e r n al t e m p era t ur e s e ns o r s. th e ext e r n al r e fer e n c e is t h e defa u l t p o w e r - u p r e fer e n c e fo r t h e d a cs. roun d rob i n measur e m ent on p o wer - u p , t h e adt7316/ad t7317/adt7 318 g o in t o r o u n d r o b i n mo de, b u t m o n i to r i n g is dis a b l e d . s e t t in g bi t c0 of c o nf igura t ion reg i st er 1 t o a 1 ena b les con v ersio n s. i t s e q u e n - c e s t h rou g h t h e t h re e ch an n e l s of v dd , i n te r n a l te m p e r a t u r e s e n s o r , an d ext e r n al t e m p era t ur e s e n s o r and t a kes a me as ur e- m e n t f r o m each. on c e t h e con v ersio n is co m p l e t e d on t h e ext e r n al t e m p er a t ur e s e n s o r , t h e de vic e lo o p s ar o u n d fo r a n o t h e r m e as ur em e n t c y cle o n al l t h r e e cha n nels. this m e t h o d o f t a kin g a m e as ur em e n t on al l t h r e e cha n ne ls i n o n e c y cle is c a l l e d rou nd ro bi n . s e tt i n g bit 4 of c o n t ro l c o n f i g u r a t i o n 2 ( a ddr ess 19 h) d i s a b l es t h e r o u nd r o b i n m o d e and i n t u r n s e t s u p t h e sin g le -cha nne l m o de . the sin g le -cha nnel m o de is w h er e o n l y o n e c h a n ne l , e . g., in t e r n al t e m p era t ur e s e ns o r , is m e as ur e d in each con v ersio n c y c l e . the t i m e t a k e n to m o n i to r a l l cha nnels wi l l n o r m a l ly n o t b e o f in t e r e st, si n c e t h e m o s t r e ce n t ly m e as ur e d value ca n b e r e ad a t an y t i m e . f o r a p plica t ion s w h er e t h e r o u nd r o b i n t i m e is i m p o r t a n t, typ i c a l t i m e s a t 25c a r e g i v e n i n t h e sp e c if ic a t i o n p a g e s. 02661-a - 043 bias diode internal sense transisto r v dd to adc v out+ v out? i n i i bias f i g u re 44. t o p l e ve l st ruc t u r e of in ter n al t e mpe r at u r e s e n s ors single- c ha nnel meas urement s e t t in g c4 o f c o n t r o l c o nf igura t io n 2 r e g i st er ena b les t h e sin g le-c hann e l m o de and al lo ws th e adt7316/adt7317/ adt7318 t o f o c u s o n o n e c h anne l o n l y . a c h anne l is s e lec t e d b y wr i t in g t o bi ts c0:c1 i n c o n t r o l c o nf igura t ion 2 r e g i st er . f o r e x am pl e, to s e l e c t t h e v dd cha nnel fo r m o ni to r i n g, wr i te to t h e c o n t r o l c o nf ig ura t io n 2 r e g i ster a n d s et c4 t o 1 (if n o t do ne s o alr e ad y), t h en w r i t e al l 0s t o b i ts c0 t o c1. al l subs e q u e n t con- versio n s wi l l b e do ne o n t h e v dd chan nel on ly . t o change t h e cha nnel s e le c t ion to t h e i n ter n a l tem p er a t ur e ch a nnel, wr i t e to t h e c o n t r o l c o nf igura t io n 2 r e g i s t er a nd s et c 0 = 1. w h en m e as ur in g in sin g le-c hann e l mo de , con v ersio n s o n t h e c h a n nel se l e ct ed oc cu r di r e ctl y a f t e r ea c h o t h e r . a n y c o m m u n i c a t i o n t o th e adt7316/adt7317/ad t7318 s t o p s t h e c o n v ersio n s, b u t t h e y are re st ar te d onc e t h e re a d or w r ite o p e r a t i o n i s c o m p l e te d . temper a t ure measurement me thod int e rnal t e mp er ature meas urem ent the adt7316 /adt7317/ad t7318 co n t a i n a n o n -c hi p ban d ga p t e m p era t ure s e n s o r w h os e o u t p ut is dig i t i ze d b y t h e o n -chi p ad c. the t e m p era t ur e da t a is st o r e d i n t h e i n t e r n al t e m p era- t u r e val u e r e g i s ter . a s b o t h p o si t i v e an d nega t i ve t e m p era t ur es ca n b e m e as ur e d , t h e tem p e ra t u r e da t a is s t o r e d i n tw os co m p le- m e n t fo r m a t , as sho w n in t a b l e 9. the t h er mal cha r ac t e r i s t ics of t h e m e as ur e m en t s e n s o r co u l d cha n g e , and t h er efo r e a n o f fs et is adde d t o t h e m e as ur e d v a lue t o ena b le t h e t r a n sfer f u n c t i o n t o ma t c h t h e t h er mal cha r ac t e r i s t ics. this o f fs et is adde d b e fo r e t h e t e m p era t ur e da t a is st o r e d . th e o f fs e t val u e us e d is s t or e d in t h e i n t e r n al t e m p era t ur e o f fs et r e g i s t er . ex t e rnal t e mp er ature meas urem ent the adt7316 /adt7317/ad t7318 ca n m e as u r e th e t e m p era- tu re of one e x te r n a l d i o d e s e ns or or d i o d e - c o n n e c t e d t r ans i s t o r . the fo r w a r d vol t a g e o f a dio d e o r dio d e - co n n e c te d t r a n sisto r , o p era t e d a t a con s t a n t c u r r en t , exhi b i ts a n e ga t i v e t e m p era t ur e co ef f i cien t o f ab o u t C2 mv/ c. u n fo r t una t e l y , t h e abs o l u te val u e o f v be va r i es f r o m de vice to de vic e , an d i ndivi d u a l ca l i b r a t io n is r e q u ir e d t o n u l l t h is o u t, s o t h e te chniq u e is u n su it abl e for mass p r o d u c t i on.
adt7316/adt7317/adt7318 rev. a | page 24 of 40 the t e c h niq u e us ed in t h e adt7316/adt731 7/adt7318 is to m e as ur e t h e chan g e in v be w h e n t h e de vice is op era t e d a t tw o dif f er en t c u r r en ts. temper a t ure v a l u e forma t on e l s b o f t h e ad c co r r es p o nds t o 0.25c. the ad c ca n t h e o r e t i cal l y m e as ur e a t e m p er a t ur e s p a n o f 255 c. th e in t e r n al t e m p era t ur e s e ns o r is gua r a n t e e d t o a lo w val u e limi t o f ? 40c. i t is p o s s i b le t o m e as ur e t h e f u l l t e m p era t ur e s p a n usin g t h e ext e r n al t e m p er a t ur e s e n s o r . the t e m p era t ur e da t a fo r m a t is sh ow n i n t a bl e 9 . t h e re su lt of t h e i n te r n a l or e x te r n a l te m p - era t ur e m e as ur e m e n ts is st o r e d in t h e t e m p era t ur e val u e r e g i s t e r s a n d i s c o m p a r e d w i th l i m i t s p r o g r a m m ed i n t o th e i n te r n a l or e x te r n a l hi g h and l o w re g i ste r s . this is g i v e n b y () n in q kt v be = ? / w h er e: k is b o l t z m a n n s co n s t a n t . q is t h e c h a r g e o n t h e ca r r ier . t is t h e a b s o l u te t e m p era t ur e i n k e lvi n . n is t h e ra t i o o f t h e tw o c u r r en t s . table 9. temp erature data format (in t ern a l an d e x tern al tem p erature) temperature digital output db9..........db0 ?40c 11 0110 0000 ?25c 11 1001 1100 ?10c 11 1101 1000 ?0.25c 11 1111 1111 0c 00 0000 0000 0.25c 00 0000 0001 10c 00 0010 1000 25c 00 0110 0100 50c 00 1100 1000 75c 01 0010 1100 100c 01 1001 0000 105c 01 1010 0100 125c 01 1111 0100 f i gur e 42 sh o w s t h e in p u t sig n a l co n d i t io nin g u s e d t o m e as ur e t h e ou t p u t o f a n ext e r n al t e m p e r a t ur e s e n s o r . this f i gur e s h o w s t h e ext e r n al s e ns o r as a dis c r e t e s u bs t r a t e t r a n si s t o r . i f a pnp t r a n sis t o r is us e d , t h e b a s e is conn e c t e d t o t h e d? in pu t an d t h e emi t t e r t o t h e d + in p u t. i f an np n t r a n sist o r is us e d , t h e e m i t - te r i s c o nne c te d to t h e d ? i n put and t h e b a s e to t h e d + i n put . w e r e co mm en d tha t a 2 n 3906 be us e d as t h e ext e r n al tra n s i s t o r . t o p r e v en t g r o u nd n o i s e i n t e r f e r in g w i t h t h e me as ur emen t, t h e more ne g a t i ve t e r m i n a l of t h e s e ns or i s no t re f e re nc e d to g r o u n d , b u t is b i as e d ab o v e g r o u nd b y an i n t e r n al dio d e a t t h e d? in pu t. a s t h e s e n s o r is o p er a t in g in a n o isy en vir o n m e n t , c 1 is p r o v ide d as a n o is e f i lt er . s e e t h e s e c t ion o n l a yo u t co n s idera t io n s fo r m o r e info r m a t io n on c1. t e m p er a t ur e c o n v ersio n f o r m u l a: to m e a s u r e ? v be , t h e s e n s o r is swi t ch e d b e tw e e n o p era t in g c u r r en ts o f i a nd n i. the r e su l t in g w a v e fo r m is p a s s e d thr o u g h a lo w-p a s s f i l t er t o r e mo v e n o is e , t h en t o a c h o p p e r st a b i l i z e d a m pl i f ier t h a t p e r f o r m s t h e f u n c t i o n s o f a m plif ica t ion a nd r e c t if ic a t ion o f t h e w a vefo r m to p r o d uc e a dc vol t a g e prop or t i on a l to ? v be . this v o l t ag e is m e as ur e d b y t h e a d c t o g i v e a t e m p era t ur e o u t p ut i n 10-b i t t w os co m p l e m e n t fo r m a t . t o f u r t h e r r e d u ce t h e ef fe c t s o f n o is e, dig i t a l f i l ter in g is p e r f o r m e d b y a v era g in g t h e r e su l t s o f 16 m e as u r em e n t c y cles. p o s i ti ve t e m p er a t u r e = ad c cod e / 4 n e ga ti ve t e m p e r a t u r e = (ad c c o d e * C 5 12)/4 *d b9 i s r e m o ved f r o m the ad c c o d e .
adt7316/adt7317/adt7318 rev. a | page 25 of 40 control configuration register 1 interrupt mask registers s t atus bits interrupt status register 1 (temp and ext. diode check) watchdog limit comparisons external temp v dd diode fault int/int enable bit int/int (latched output) s t atus bit interrupt status register 2 (v dd ) internal temp s/w reset read reset 02661-a - 044 f i gur e 4 5 . ad t7 31 6/ ad t7 31 7/ ad t7 318 inte rr upt str u ctur e interrupt s the m e as ur e d r e s u l t s f r o m t h e i n t e r n al t e m p era t ur e s e n s o r , ext e r n al t e m p er a t ur e s e n s o r , and t h e v dd pi n are c o m p are d w i t h th e t hi g h /v hi g h ( g re a t e r t h an c o m p ar i s on ) a n d t low /v low (les s tha n o r eq u a l t o co m p a r is o n ) limi ts. an in t e r r u p t o c c u r s if t h e m e as ur em e n t ex ceed s o r eq uals th e li mi t r e gi s t e r s . t h ese li m i ts a r e s t o r e d i n o n -chi p r e g i st ers. n o t e t h a t t h e li mi t r e g i st ers a r e 8 b i t s lo ng, w h i l e t h e con v ersio n r e s u l t s a r e 10 b i t s lo ng. i f t h e limi ts a r e n o t mas k e d o u t, t h e n a n y o u t-o f -limi t co m p a r is o n s g e n e ra t e f l a g s t h a t a r e s t o r e d i n i n t e r r u p t s t a t u s 1 r e g i s t er ( a ddr ess = 00h) a nd i n ter r u p t s t a t us 2 r e g i ster ( a ddr ess = 01 h) . o n e or more out - of - l i m it re su lt s w i l l c a u s e t h e i n t / int output t o p u l l ei t h er hig h o r lo w dep e ndin g o n t h e o u t p u t p o la r i ty s e t t ing. i t is g o o d desig n p r ac tic e t o mas k o u t in t e r r u p ts f o r cha nnels t h a t a r e o f n o co ncer n to t h e a p pli c a t io n. f i gur e 45 sh o w s th e in t e r r u p t s t r u c t ur e f o r th e adt7316/ adt7317/ adt7318. i t g i v e s a b l o c k dia g ra m r e p r es en ta tio n o f h o w t h e va r i o u s m e as ur emen t cha nne ls a f fe c t t h e i n t/ int pi n .
adt7316/adt7317/adt7318 rev. a | page 26 of 40 registers the adt7316 /adt7317/ad t7318 co n t a i n r e g i s t ers tha t a r e u s e d to store t h e re su lt s of e x te r n a l and i n te r n a l te m p e r a t u r e m e as ur e m en ts, v dd val u e m e asur em e n ts, hig h a nd lo w tem p - era t ur e and s u pply v o l t a g e limi t s . th e y als o s e t o u t p ut d a c vol t a g e le vels, c o nf igur e m u l t i p ur p o s e p i n s , and gener a l l y co n t r o l t h e de vi ce . a de s c r i p t ion o f t h e s e r e g i sters fol l o w s. the r e g i s t er ma p is divide d i n t o r e g i s t ers o f 8 b i ts. e a ch r e g i st er has i t s o w n i ndivi d u a l ad dr ess, b u t s o me co n s ist o f da t a t h a t is link e d wi t h o t her r e g i s t ers. th e s e r e g i s t ers h o ld t h e 10 -b i t co n v ersio n r e s u l t s o f m e as ur e m en ts t a k e n on t h e t e m p era t ur e a nd v dd cha nnels. f o r exa m ple , t h e 8 m s bs o f t h e v dd me asur e - m e n t a r e st o r e d in reg i st er a ddr es s 06h, w h i l e t h e 2 ls b s a r e s t o r e d i n reg i s ter a ddr es s 03 h. the li nk i n v o lve d b e tw e e n t h es e typ e s o f r e g i s t ers is t h a t w h en t h e lsb r e g i s t er is r e ad f i rs t t h e n th e ms b r e gi s t er s a s soci a t ed w i th tha t l s b r e gis t e r a r e loc k ed o u t t o p r e v en t an y u p da t e s. t o unlo ck t h e s e m s b r e g i s t ers, t h e u s e r h a s on ly to re a d a n y one of t h e m , w h i c h w i l l h a ve t h e e f f e c t o f unlo c k in g al l p r evio us l y lo c k ed o u t ms b r e g i s t ers. s o fo r th e exa m ple g i v e n ab o v e, if reg i s ter 03h was r e ad f i rs t, t h en m s b reg i st ers 06h and 07h w o u l d b e lo ck e d o u t t o p r e v en t an y u p da t e s t o t h em. i f r e g i s t er 06h was r e ad , t h en t h is r e g i s t er and r e gi st e r 07h w o uld be s u bseq uen t l y unloc k e d . l o c k as s o ci at e d m s b re g i s t e r s fir s t r e a d co m m and ls b r e g i st er ou tp u t dat a 04 66 1- a - 04 6 f i g u re 46. phas e 1 of 1 0 -bit r e ad unl o ck as s o ci at e d m s b re g i s t e r s s e co nd re ad co m m a n d ms b r e g i st er ou tp u t dat a 04 66 1- a - 04 7 f i g u re 47. phas e 2 of 1 0 -bit r e ad i f a n ms b r e g i ster is r e ad f i rs t, i t s co r r es p o ndi ng ls b r e g i s t er is n o t lo ck e d o u t, le a v in g t h e us er wi t h t h e o p t i on o f j u s t r e adin g b a ck 8 b i ts (msb) o f a 10-b i t con v ersio n r e s u lt. re adi n g a n msb r e g i s t er f i rs t do es n o t lo ck o u t o t h e r ms b r e g i st ers, a nd li k e wis e , r e ading a n ls b r e g i st e r f i rs t do es n o t l o ck o u t o t h e r ls b r e g i s t ers. table 10. list o f adt7316/ adt7317/adt73 18 registers rd/wr addres s n a m e p o w e r - o n defa u l t 00h interrupt status 1 00h 01h interrupt status 2 00h 02h reserved 00h 03h internal t e mp and v dd lsbs 00h 04h external temp ls bs 00h 05h reserved 00h 06h v dd msbs xxh 07h internal temp m s bs 00h 08h external temp m s bs 00h 09hC 0 fh reserved 00h 10h dac a ls bs (adt 731 6/a d t7 317 o n ly) 00h 11h dac a ms bs 00h 12h dac b lsbs (adt 731 6/a d t7 317 o n ly) 00h 13h dac b msbs 00h 14h d a c c lsbs (adt 731 6/a d t7 317 o n ly) 00h 15h dac c msbs 00h 16h dac d lsbs (adt 731 6/a d t7 317 o n ly) 00h 17h dac d msbs 00h 18h control configuration 1 00h 19h control configuration 2 00h 1ah control configuration 3 00h 1bh dac configuration 00h 1ch ldac configuration 00h 1dh interrupt mask 1 00h 1eh interrupt mask 2 00h 1fh internal temp of fset 00h 20h external temp of fset 00h 21h internal anal og temp offset d8h 22h external anal og t e mp offset d8h 23h v dd v hig h limit c7h 24h v dd v lo w limit 62h 25h internal t hig h limit 64h 26h internal t lo w limi t c9h 27h external t hig h lim i t ffh 28h external t low limit 00h 29hC 4 ch reserved 4dh device i d 01h/ 09h /0 5h 4eh manufacturers i d 41h 4fh silico n revision 04h 50hC 7 eh reserved 00h 7f spi lo ck status 00h 80Cff reserved 00h
adt7316/adt7317/adt7318 rev. a | page 27 of 27 interrupt status 1 register (read-only) [add. = 00h] this 8-bit read-only register reflects the status of some of the interrupts that can cause the int/ int pin to go active. this register is reset by a read operation, provided that any out-of- limit event has been corrected. it is also reset by a software reset. table 11. interrupt status 1 register d7 d6 d5 d4 d3 d2 d1 d0 n/a n/a n/a 0* 0* 0* 0* 0* * default settings at power-up. table 12. bit function d0 1 when internal temperature value exceeds t high limit. any internal temperature reading gr eater than the limit set will cause an out-of-limit event. d1 1 when internal temperature value exceeds t low limit. any internal temperature reading less than or equal to the limit set will cause an out-of-limit event. d2 1 when external temperature value exceeds t high limit. the default value for this limit regi ster is C1c, so any external temperature reading greater than the limit set will cause an out-of-limit event. d3 1 when external temperature value exceeds t low limit. the default value for this limit regi ster is 0c, so any external temperature reading less than or equal to the limit set will cause an out-of-limit event. d4 1 indicates a fault (open or short) for the external temperature sensor. interrupt status 2 register (read-only) [add. = 01h] this 8-bit read-only register reflects the status of the v dd interrupt that can cause the int/ int pin to go active. this register is reset by a read operation provided that any out-of- limit event has been corrected. it is also reset by a software reset. table 13. interrupt status 2 register d7 d6 d5 d4 d3 d2 d1 d0 n/a n/a n/a 0* n/a n/a n/a n/a * default settings at power-up. table 14. bit function d4 1 when v dd value is greater than corresponding v high limit. 1 when v dd is less than or equal to corresponding v low limit. internal temperature value/v dd va lu e re g i ster lsbs (re a d- only) [add. = 03h] this 8-bit read-only register stores the 2 lsbs of the 10-bit temperature reading from the internal temperature sensor and the 2 lsbs of the 10-bit supply voltage reading. table 15. internal temperature/v dd lsbs d7 d6 d5 d4 d3 d2 d1 d0 n/a n/a n/a n/a v1 lsb t1 lsb n/a n/a n/a n/a 0* 0* 0* 0* * default settings at power-up. table 16. bit function d0 lsb of internal temperature value. d1 b1 of internal temperature value. d2 lsb of v dd value. d3 b1 of v dd value. external temperature value register lsbs (read-only) [add. = 04h] this 8-bit read-only register stores the 2 lsbs of the 10-bit temperature reading from the external temperature sensor. table 17. external temperature lsbs d7 d6 d5 d4 d3 d2 d1 d0 n/a n/a n/a n/a n/a n/a t1 lsb n/a n/a n/a n/ a n/a n/a 0* 0* * default settings at power-up. table 18. bit function d0 lsb of external temperature value. d1 b1 of external temperature value. v dd value register msbs (read-only) [add. = 06h] this 8-bit read-only register stores the supply voltage value. the 8 msbs of the 10-bit value are stored in this register. table 19. v dd value msbs d7 d6 d5 d4 d3 d2 d1 d0 v9 v8 v7 v6 v5 v4 v3 v2 x* x* x* x* x* x* x* x* *loaded with v dd value after power-up. internal temperature value register msbs (read-only) [add. = 07h] this 8-bit read-only register stores the internal temperature value from the internal temperature sensor in twos complement format. the 8 msbs of the 10-bit value are stored in this register. table 20. internal temperature value msbs d7 d6 d5 d4 d3 d2 d1 d0 t9 t8 t7 t6 t5 t4 t3 t2 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up.
adt7316/adt7317/adt7318 rev. a | page 28 of 40 external temperature value register msbs (read-only) [add. = 08h] this 8-bit read-only register stores the external temperature value from the external temperature sensor in twos complement format. the 8 msbs of the 10-bit value are stored in this register. table 21. external temperature value msbs d7 d6 d5 d4 d3 d2 d1 d0 t9 t8 t7 t6 t5 t4 t3 t2 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up. dac a register lsbs (read/write) [add. = 10h] this 8-bit read/write register contains the 4/2 lsbs of the adt7316/adt7317 dac a word, respectively. the value in this register is combined with the value in the dac a register msbs and converted to an analog voltage on the v out -a pin. on power-up, the voltage output on the v out -a pin is 0 v. table 22. dac a (adt7316) lsbs d7 d6 d5 d4 d3 d2 d1 d0 b3 b2 b1 lsb n/a n/a n/a n/a 0* 0* 0* 0* n/a n/a n/a n/a * default settings at power-up. table 23. dac a (adt7317) lsbs d7 d6 d5 d4 d3 d2 d1 d0 b1 lsb n/a n/a n/a n/a n/a n/a 0* 0* n/a n/a n/a n/a n/a n/a * default settings at power-up. dac a register msbs (read/write) [add. = 11h] this 8-bit read/write register contains the 8 msbs of the dac a word. the value in this register is combined with the value in the dac a register lsbs and converted to an analog voltage on the v out -a pin. on power-up, the voltage output on the v out -a pin is 0 v. table 24. dac a msbs d7 d6 d5 d4 d3 d2 d1 d0 msb b8 b7 b6 b5 b4 b3 b2 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up. dac b register lsbs (read/write) [add. = 12h] this 8-bit read/write register contains the 4/2 lsbs of the adt7316/adt7317 dac b word, respectively. the value in this register is combined with the value in the dac b register msbs and converted to an analog voltage on the v out -b pin. on power-up, the voltage output on the v out -b pin is 0 v. table 25. dac b (adt7316) lsbs d7 d6 d5 d4 d3 d2 d1 d0 b3 b2 b1 lsb n/a n/a n/a n/a 0* 0* 0* 0* n/a n/a n/a n/a * default settings at power-up. table 26. dac b (adt7317) lsbs d7 d6 d5 d4 d3 d2 d1 d0 b1 lsb n/a n/a n/a n/a n/a n/a 0* 0* n/a n/a n/a n/a n/a n/a * default settings at power-up. dac b register msbs (read/write) [add. = 13h] this 8-bit read/write register contains the 8 msbs of the dac b word. the value in this register is combined with the value in the dac b register lsbs and converted to an analog voltage on the v out -b pin. on power-up, the voltage output on the v out -b pin is 0 v. table 27. dac b msbs d7 d6 d5 d4 d3 d2 d1 d0 msb b8 b7 b6 b5 b4 b3 b2 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up. dac c register lsbs (read/write) [add. = 14h] this 8-bit read/write register contains the 4/2 lsbs of the adt7316/adt7317 dac c word, respectively. the value in this register is combined with the value in the dac c register msbs and converted to an analog voltage on the v out -c pin. on power-up, the voltage output on the v out -c pin is 0 v. table 28. dac c (adt7316) lsbs d7 d6 d5 d4 d3 d2 d1 d0 b3 b2 b1 lsb n/a n/a n/a n/a 0* 0* 0* 0* n/a n/a n/a n/a * default settings at power-up. table 29. dac c (adt7317) lsbs d7 d6 d5 d4 d3 d2 d1 d0 b1 lsb n/a n/a n/a n/a n/a n/a 0* 0* n/a n/a n/a n/a n/a n/a * default settings at power-up. dac c register msbs (read/write) [add. = 15h] this 8-bit read/write register contains the 8 msbs of the dac c word. the value in this register is combined with the value in the dac c register lsbs and converted to an analog voltage on the v out -c pin. on power-up, the voltage output on the v out -c pin is 0 v.
adt7316/adt7317/adt7318 rev. a | page 29 of 40 table 30. dac c msbs d7 d6 d5 d4 d3 d2 d1 d0 msb b8 b7 b6 b5 b4 b3 b2 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up. dac d register lsbs (read/write) [add. = 16h] this 8-bit read/write register contains the 4/2 lsbs of the adt7316/adt7317 dac d word, respectively. the value in this register is combined with the value in the dac d register msbs and converted to an analog voltage on the v out -d pin. on power-up, the voltage output on the v out -d pin is 0 v. table 31. dac d (adt7316) lsbs d7 d6 d5 d4 d3 d2 d1 d0 b3 b2 b1 lsb n/a n/a n/a n/a 0* 0* 0* 0* n/a n/a n/a n/a * default settings at power-up. table 32. dac d (adt7317) lsbs d7 d6 d5 d4 d3 d2 d1 d0 b1 lsb n/a n/a n/a n/a n/a n/a 0* 0* n/a n/a n/a n/a n/a n/a * default settings at power-up. dac d register msbs (read/write) [add. = 17h] this 8-bit read/write register contains the 8 msbs of the dac d word. the value in this register is combined with the value in the dac d register lsbs and converted to an analog voltage on the v out -d pin. on power-up, the voltage output on the v out -d pin is 0 v. table 33. dac d msbs d7 d6 d5 d4 d3 d2 d1 d0 msb b8 b7 b6 b5 b4 b3 b2 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up. control configuration 1 register (read/write) [add. = 18h] this configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the adt7316/ adt7317/adt7318. table 34. control configuration 1 d7 d6 d5 d4 d3 d2 d1 d0 pd c6 c5 c4 c3 c2 c1 c0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up. table 35. bit function c0 this bit enables/disables conversions in round robin and single-channel mode. adt7316/adt7317/adt7318 power up in round robin mo de but monitoring is not initiated until this bit is set. default = 0. 0 = stop monitoring. 1 = start monitoring. c1:4 reserved. only write 0s. c5 0 = enable int/ int output. 1 = disable int/ int output. c6 configures int/ int output polarity. 0 = active low. 1 =active high. pd power-down bit. setting this bit to 1 puts the adt7316/ adt7317/adt7318 into standb y mode. in this mode, both adc and dacs are fully powered down, but serial interface is still operational. to power up the part again, write a 0 to this bit. control configuration 2 register (read/write) [add. = 19h] this configuration register is an 8-bit read/write register that is used to set up some of the operating modes of the adt7316/ adt7317/adt7318. table 36. control configuration 2 d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up. table 37. bit function c1:0 in single-channel mode, these bits select between v dd , the internal temperature sensor, and the external temperature sensor for co nversion. default is v dd . 00 = v dd . 01 = internal temperature sensor. 10 = external temperature sensor. 11 = reserved. c2:c3 reserved. c4 selects between single-channel and round robin conversion cycle. default is round robin. 0 = round robin. 1 = single channel. c5 default condition is to average every measurement on all channels 16 times. this bit disables this averaging. channels affected are temperature and v dd . 0 = enable averaging. 1 = disable averaging. c6 smbus timeout on the serial clock puts a 25 ms limit on the pulse width of the clock. ensures that a fault on the master scl does not lock up the sda line. smbus timeout. 0 = disable. 1 = enable smbus timeout. c7 software reset. setting this bit to a 1 causes a software reset. all registers and dac outputs will reset to their default settings.
adt7316/adt7317/adt7318 rev. a | page 30 of 40 control configuration 3 register (read/write) [add. = 1ah] this configuration register is an 8-bit read/write register that is used to set up some of the operating modes of the adt7316/ adt7317/adt7318. table 38. control configuration 3 d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up. table 39. bit function c0 selects between fast and normal adc conversion speeds for all three monitoring channels. 0 = adc clock at 1.4 khz. 1 = adc clock at 22.5 khz. d+ and d ? analog filters are disabled. c1 on the adt7316 and adt7317, this bit selects between 8- bits and 10-bits dac output resolution on the thermal voltage output feature. defaul t = 8 bits. this bit has no effect on the adt7318 output si nce this part has only an 8- bit dac. in the adt7318 case, write 0 to this bit. 0 = 8 bits resolution. 1 = 10 bits resolution. c2 reserved. only write 0. c3 0 = ldac pin controls updating of dac outputs. 1 = dac configuration register and ldac configuration register control the updating of the dac outputs. c4 reserved. only write 0. c5 setting this bit selects dac a voltage output to be proportional to the internal temperature measurement. c6 setting this bit selects dac b voltage output to be proportional to the external temperature measurement. c7 reserved. only write 0. dac configuration register (read/write) [add. = 1bh] this configuration register is an 8-bit read/write register that is used to control the output ranges of all four dacs and to control the loading of the dac registers if the ldac pin is disabled (bit c3 = 1, control configuration 3 register). table 40. dac configuration d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up. table 41. bit function d0 selects the output range of dac a. 0 = 0 v to v ref . 1 = 0 v to 2 v ref . d1 selects the output range of dac b. 0 = 0 v to v ref . 1 = 0 v to 2 v ref . d2 selects the output range of dac c. 0 = 0 v to v ref . 1 = 0 v to 2 v ref . d3 selects the output range of dac d. 0 = 0 v to v ref . 1 = 0 v to 2 v ref . d5:d4 00 msb write to any dac register will generate ldac command, which updates that dac only. 01 msb write to dac b or dac d register will generate ldac command, which updates dacs a, b or dacs c, d, respectively. 10 msb write to dac d register will generate ldac command, which updates all 4 dacs. 11 ldac command generated from ldac register. d6 setting this bit allows the external v ref to bypass the reference buffer when supplying dacs a and b. d7 setting this bit allows the external v ref to bypass the reference buffer when supplying dacs c and d. ldac configuration register (write-only) [add. = 1ch] this configuration register is an 8-bit write register that is used to control the updating of the quad dac outputs if the ldac pin is disabled and bits d4 and d5 of dac configuration register are both set to 1. it also selects either the internal or external v ref for all four dacs. bits d0Cd3 in this register are self clearing, i.e., reading back from this register will always give 0s for these bits. table 42. ldac configuration d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up. table 43. bit function d0 writing a 1 to this bit will generate the ldac command to update the dac a output only. d1 writing a 1 to this bit will generate the ldac command to update the dac b output only. d2 writing a 1 to this bit will generate the ldac command to update the dac c output only. d3 writing a 1 to this bit will generate the ldac command to update the dac d output only. d4 selects either internal v ref or external v ref -ab for dacs a and b. 0 = external v ref . 1 = internal v ref . d5 selects either internal v ref or external v ref -cd for dacs c and d. 0 = external v ref . 1 = internal v ref . d6:d7 reserved. only write 0s.
adt7316/adt7317/adt7318 rev. a | page 31 of 31 interrupt mask 1 register (read/write) [add. = 1dh] this mask register is an 8-bit read/write register that can be used to mask out any interrupts that can cause the int/ int pin to go active. table 44. interrupt mask 1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up. table 45. bit function d0 0 = enable internal t high interrupt. 1 = disable internal t high interrupt. d1 0 = enable internal t low interrupt. 1 = disable internal t low interrupt. d2 0 = enable external t high interrupt. 1 = disable external t high interrupt. d3 0 = enable external t low interrupt. 1 = disable external t low interrupt. d4 0 = enable external temp erature fault interrupt. 1 = disable external temp erature fault interrupt. d5:d7 reserved. only write 0s. interrupt mask 2 register (read/write) [add. = 1eh] this mask register is an 8-bit read/write register that can be used to mask out any interrupts that can cause the int/ int pin to go active. table 46. interrupt mask 2 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up. table 47. bit function d0:d3 reserved. only write 0s. d4 0 = enable vdd interrupts. 1 = disable vdd interrupts. d5:d7 reserved. only write 0s. internal temperature offset register (read/write) [add. = 1fh] this register contains the offset value for the internal temperature channel. a twos complement number can be written to this register which is then added to the measured result before it is stored or co mpared to limits. in this way, a one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. from a software point of view, this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. as it is an 8-bit register, the temperature resolution is 1c. table 48. internal temperature offset d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0 0* * default settings at power-up. external temperature offset register (read/write) [add. = 20h] this register contains the offset value for the external temperature channel. a twos complement number can be written to this register which is then added to the measured result before it is stored or comp ared to limits. in this way, one- point calibration can be done whereby the whole transfer function of the channel can be moved up or down. from a software point of view, this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. as it is an 8-bit register, the temperature resolution is 1c. table 49. external temperature offset d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up. internal analog temperature offset register (read/write) [add. = 21h] this register contains the offset value for the internal thermal voltage output. a twos complement number can be written to this register which is then added to the measured result before it is converted by dac a. varying the value in this register has the affect of varying the temperature span. for example, the output voltage can represent a temperature span of ?128c to +127c or even 0c to 127c. in essence, this register changes the position of 0 v on the temperature scale. anything other than ?128c to +127c will produce an upper dead band on the dac a output. as it is an 8-bit register, the temperature resolution is 1c. the default value is ?40c. table 50. internal analog temperature offset d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 0* 1* 1* 0* 0* 0* * default settings at power-up. external analog temperature offset register (read/write) [add. = 22h] this register contains the offset value for the external thermal voltage output. a twos complement number can be written to this register which is then added to the measured result before it is converted by dac b. varying the value in this register has the affect of varying the temperature span. for example, the output
adt7316/adt7317/adt7318 rev. a | page 32 of 40 voltage can represent a temperature span of ?128c to +127c or even 0c to 127c. in essence, this register changes the posi- tion of 0 v on the temperature scale. anything other than ?128c to +127c will produce an upper dead band on the dac b output. as it is an 8-bit register, the temperature reso- lution is 1c. the default value is ?40c. table 51. external analog temperature d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 0* 1* 1* 0* 0* 0* * default settings at power-up. v dd v high limit register (read/write) [add. = 23h] this limit register is an 8-bit read/write register which stores the v dd upper limit that will cause an interrupt and activate the int/ int output (if enabled). for this to happen, the measured v dd value has to be greater than the value in this register. the default value is 5.46 v. table 52. v dd v high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 0* 0* 0* 1* 1* 1* * default settings at power-up. v dd v low limit register (read/write) [add. = 24h] this limit register is an 8-bit read/write register which stores the v dd lower limit that will cause an interrupt and activate the int/ int output (if enabled). for this to happen, the measured v dd value has to be less than or equal to the value in this register. the default value is 2.7 v table 53. v dd v low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 1* 1* 0* 0* 0* 1* 0* * default settings at power-up. internal t high limit register (read/write) [add. = 25h] this limit register is an 8-bit read/write register which stores the twos complement of the internal temperature upper limit that will cause an interrupt and activate the int/ int output (if enabled). for this to happen, the measured internal temperature value has to be greater than the value in this register. as it is an 8-bit register the temperature resolution is 1c. default value is +100c. table 54. internal t high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 1* 1* 0* 0* 1* 0* 0* * default settings at power-up. internal t low limit register (read/write) [add. 26h] this limit register is an 8-bit read/write register which stores the twos complement of the internal temperature lower limit that will cause an interrupt and activate the int/ int output (if enabled). for this to happen, the measured internal temperature value has to be more negative than or equal to the value in this register. as it is an 8-bit register, the temperature resolution is 1c. the default value is ?55c. table 55. internal t low limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 0* 0* 1* 0* 0* 1* * default settings at power-up. external t high limit register (read/write) [add. = 27h] this limit register is an 8-bit read/write register which stores the twos complement of the external temperature upper limit that will cause an interrupt and activate the int/ int output (if enabled). for this to happen, the measured external temperature value has to be greater than the value in this register. as it is an 8-bit register, the temperature resolution is 1c. the default value is ?1c. table 56. external t high limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1* 1* 1* 1* 1* 1* 1* 1* * default settings at power-up. external t low limit register (read/write) [add. = 28h] this limit register is an 8-bit read/write register which stores the twos complement of the external temperature lower limit that will cause an interrupt and activate the int/ int output (if enabled). for this to happen, the measured external temperature value has to be more negative than or equal to the value in this register. as it is an 8-bit register, the temperature resolution is 1c. the default value is 0c. table 57. external t lo w limit d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0* 0* 0* 0* 0* 0* 0* 0* * default settings at power-up. device id register (read-only) [add. = 4dh] this 8-bit read-only register indicates which part the device is in the model range. adt7316 = 01h, adt7317 = 09h, and adt7318 = 05h. manufacturers id register (read-only) [add. = 4eh] this register contains the manufacturers identification number. adis id is 41h.
adt7316/adt7317/adt7318 rev. a | page 33 of 40 02 66 1- a - 04 9 cs sd a sc l add v dd v dd i 2 c a ddre s s = 10 01 000 10 k ? 10 k ? a d t 7316/ a d t 7317/ a d t 7318 s i li c o n re v i si o n reg i st er ( r e a d-on l y ) [a d d . = 4f h ] this r e g i ster is divide d i n to t h e 4 ls bs r e p r es e n t i ng t h e s t ep pin g and t h e 4 ms bs r e p r es en t i n g t h e v e rsi o n. th e st ep ping c o n t ai ns t h e m a n u f a c t u r e r s c o d e f o r m i nor re v i s i ons or s t ep p i n g s t o t h e silico n. the v e rsio n is t h e ad t7316/adt7317 / adt7318 v e rsio n n u m b er . sp i l o c k st atu s re g i s t er ( r e a d - o n l y ) [ a d d . = 7 f h ] b i t d0 (ls b ) o f t h is r e ad-o nly r e g i s t er i ndic a t e s w h et h e r t h e spi in t e r f ace is lo cke d o r n o t. w r i t i n g t o t h is r e g i s ter wi l l c a us e t h e de vice to ma lf u n c t ion. t h e def a u l t va l u e is 00h . f i g u re 48. t y pic a l i 2 c inter f ac e c o nnec t ion 02 66 1- a - 05 0 a d t 7316/ a d t 7317/ a d t 7318 sc l k do ut cs v dd l o ck a n d sel ec t spi s p i f r a m in g ed g e 82 0 ? 820 ? 820 ? di n 0 = i 2 c i n te r f a c e. 1 = s p i i n t e rfa c e s e lec t ed a n d l o c k ed . f i gure 49. t y pic a l s p i inter f ac e conn ec tion 02 66 1- a - 0 4 8 a b cs ( s t art h i g h ) spi l o c k ed o n t h i rd ri s i n g e d g e c spi f r a m i n g ed g e a b cs ( s t art l o w ) s p i l o cke d o n t h i r d ri s i ng e d g e c s p i f r a m in g ed g e f i g u re 50. s e ri al int e r f ace s e lec t ing and l o ck ing s p i proto c o l 02661-a - 051 0 1 r/w scl sda frame 1 serial bus address byte frame 2 address pointer register byte ack. by adt7316/adt7317/adt7318 ack. by adt7316/adt7317/adt7318 stop by master start by master 0 0 1 a 2 a 1 a p 7 p6 p5 p4 p3 p2 p1 p0 9 1 9 1 f i g u re 51. i 2 cwriti n g to the address p o i n ter regi ster to sel e ct a regi st er fo r a subseque nt r e a d oper ati o n
adt7316/adt7317/adt7318 rev. a | page 34 of 40 serial interface there are two serial interfaces that can be used on this part, i 2 c and spi. the device will power up with the serial interface in i 2 c mode, but it is not locked into this mode. to stay in i 2 c mode, it is recommended that the user ties the cs line to either v cc or gnd. it is not possible to lock the i 2 c mode, but it is possible to select and lock the spi mode. to select and lock the interface into the spi mode, a number of pulses must be sent down the cs (pin 4) line. the following section describes how this is done. once the spi communication protocol has been locked in, it cannot be unlocked while the device is still powered up. bit d0 of spi lock status register (address = 7fh) is set to 1 when a successful spi interface lock has been accomplished. to reset the serial interface, the user must power down the part and power up again. a software reset does not reset the serial interface. serial interface selection the cs line controls the selection between i 2 c and spi. figure 49 shows the selection process necessary to lock the spi interface mode. if the user wants to communicate to the adt7316/adt7317/ adt7318 using the spi protocol, send three pulses down the cs line as shown in figure 49. on the third rising edge (marked as c in figure 49), the part selects and locks the spi interface. the user is now limited to communicating to the device using the spi protocol. as per most spi standards, the cs line must be low during every spi communication to the adt7316/adt7317/ adt7318 and high all other times. typical examples of how to connect up the dual interface as i 2 c or spi is shown in figure 48 and figure 49. the following sections describe in detail how to use the i 2 c and spi protocols associated with the adt7316/adt7317/ adt7318. i 2 c serial interface like all i 2 c compatible devices, the adt7316/adt7317/ adt7318 have a 7-bit serial address. the 4 msbs of this address for the adt7316/adt7317/adt7318 are set to 1001. the 3 lsbs are set by pin 11, add. the add pin can be con- figured three ways to give three different address options: low, floating, and high. setting the add pin low gives a serial bus address of 1001 000, leaving it floating gives the address 1001 010, and setting it high gives the address 1001 011. the recommended pullup resistor value is 10 k?. there is a programmable smbus timeout. when this is enabled the smbus will timeout after 25 ms of no activity. to enable it, set bit 6 of control configuration 2 register. the power-up default is with the smbus timeout disabled. the adt7316/adt7317/adt7318 support smbus packet error checking (pec) and its use is optional. it is triggered by supplying the extra clocks for the pec byte. the pec is calculated using crc-8. the frame clock sequence (fcs) conforms to crc-8 by the polynomial: c(x) = x 8 + x 2 + x 1 + 1 consult smbus specification (www.smbus.org) for more information. the serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line sda while the serial clock line scl remains high. this indicates that an address/data stream will follow. all slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, consisting of a 7-bit address (msb first) plus a r/ w bit, which determines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. all other devices on the bus now remain idle, while the selected device waits for data to be read from or written to it. if the r/ w bit is a 0, the master will write to the slave device. if the r/ w bit is a 1, the master will read from the slave device. 2. data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an acknowledge bit from the receiver of data. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal. 3. when all data bytes have been read or written, stop conditions are established. in write mode, the master will pull the data line high during the 10th clock pulse to assert a stop condition. in read mode, the master device will pull the data line high during the low period before the 9th clock pulse. this is known as no acknowledge. the master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. any number of bytes of data may be transferred over the serial bus in one operation but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation.
adt7316/adt7317/adt7318 rev. a | page 35 of 40 the i 2 c addr es s s et u p b y t h e a d d p i n is n o t l a t c h e d b y t h e d e v i ce un til a f t e r th i s a d d r e s s ha s been sen t tw ice . o n t h e e i g h t h scl c y cle o f t h e s e co nd va lid comm un ic a t io n, t h e s e r i a l b u s addr es s is la t c h e d i n . this is t h e scl c y cle dir e c t ly a f t e r t h e de vice has s e e n i t s o w n i 2 c s e r i al b u s addr es s. an y s u bs e q ue n t c h a n g e s o n this p i n wil l ha v e n o ef f e c t o n th e i 2 c s e r i al b u s addr ess. w r iting t o the ad t731 6 / ad t7 317 /ad t 731 8 d e p e nding o n t h e r e g i st er b e ing wr i t t e n t o , t h e r e a r e tw o dif- f e r e n t wr i t es f o r th e adt7316/adt7317/ad t7318. i t is n o t p o s s i b l e t o do a b l o c k wr i te t o t h is p a r t , i . e ., n o i 2 c a u t o - i n cr em en t . w r iting t o the a d dress p o i n t e r r egist e r f o r a subse q uent re a d i n ord e r to re a d d a t a f rom a p a r t i c u l ar re g i ste r , t h e a d d r e s s p o in t e r r e g i s t er m u s t co n t a i n t h e addr ess o f t h a t r e g i s t er . i f i t do es n o t, t h e co r r e c t addr es s m u s t b e wr i t ten to t h e addr es s p o in t e r r e g i s t er b y p e r f o r min g a sin g le- b yt e wr i te o p era t ion, as s h o w n i n f i gur e 51. the wr i t e op era t ion co n s is t s o f t h e s e r i a l b u s addr es s fol l o w e d b y t h e addr es s p o i n t e r b y t e . n o da t a is wr i t t e n t o an y o f t h e da t a reg i s ters. a r e ad o p era t io n is t h en p e r f or me d to re a d t h e re g i s t e r . w r iting d a ta to a r e gist er al l r e g i s t ers a r e 8-b i t r e g i s t ers s o o n ly o n e b y te o f da t a can b e wr i t t e n t o e a ch r e g i s t er . w r i t i n g a sin g le b y te o f da t a t o on e o f t h es e r e ad/ w r i te r e g i s t ers co n s ists o f t h e s e r i al b u s addr es s, t h e da t a r e g i s t er addr es s wr i t t e n t o t h e addr es s p o i n t e r r e g i s t er , fol l o w e d b y t h e d a t a b y te w r i tte n to t h e s e l e c t e d da t a re g i st e r . this is i l l u s t ra t e d i n f i gur e 52. t o wr i te t o a dif f er en t r e g i s t er , anot he r s t ar t or re p e a t e d s t ar t i s re qu i r e d . i f mo re t h an o n e b y te o f da t a is s e n t i n o n e co m m uni c a t ion o p er a t ion, t h e a ddr ess e d r e g i s t e r w i ll be r e pe a t e d l y l o a d ed u n ti l th e l a s t d a t a b y t e h a s been sen t . r e a d ing d a ta f r o m the a d t 7 3 16/ a d t 7 31 7/ a d t7 3 18 readin g da t a f r o m t h e ad t73 16/7317/7318 is do n e in a on e b y t e op era t ion. re adi n g b a ck t h e co n t e n ts o f a reg i s t er is sh o w n in f i gur e 56. the r e g i s t er addr e s s p r e v io us ly had b e en s et u p b y a sin g le b y te wr i t e o p era t io n t o t h e addr es s p o i n t e r r e g i s t er . t o re a d f rom anot he r re g i ste r , w r ite to t h e a d d r e s s p o i n te r re g i ste r a g a i n t o s e t u p t h e r e l e van t r e g i s t er addr es s. ther efo r e , b l o c k r e ads a r e n o t p o s s i b le, i . e . , n o i 2 c a u t o - i n c r e m e n t . spi serial interf a c e the s p i s e r i a l in t e r f ac e o f the adt7316/ad t7317/adt7318 c o ns i s t s of f o u r w i re s , cs , sclk, d i n, an d d o ut . the cs is us ed t o s e lec t t h e de vic e w h en m o r e than o n e de vice is co nn e c te d to t h e s e r i a l clo c k and da t a li n e s. t h e cs is als o us ed t o d i s t in g u i s h b e t w een a n y tw o se pa ra t e se rial co m m un ica t i o n s (s ee f i gur e 58). the sclk is us ed t o c l o c k da t a in and o u t o f t h e p a r t . th e d i n li n e is us e d t o wr i t e t o t h e r e g i s t e r s a n d t h e d o ut l i n e is u s ed t o r e ad da t a bac k f r o m t h e r e g i s t er s. the r e co mm ended p u l l -u p r e sis t o r val u e is betw een 500 ? t o 820 ? the p a r t o p era tes in a s l a v e mo de an d r e q u ir es a n ext e r n al ly a p plie d s e r i al cl o c k t o t h e sc l k i n p u t. th e s e r i al in t e r f ace is de s i g n e d to a l l o w t h e p a r t to b e i n te r f a c e d to s y ste m s t h a t p r o v id e a s e r i a l clo c k t h a t is sy nchr o n ize d t o t h e s e r i a l da t a . ther e a r e tw o t y p e s o f s e r i al o p era t io n s , a r e ad a nd a wr i t e . c o mmand w o r d s a r e us e d to d i st in gui s h b e twe e n a r e a d an d a wr i te o p era t io n. th e s e co mmand w o r d s a r e g i v e n i n t a b l e 58. a ddr ess a u t o - i ncr e m e n t is p o ss ib le in s p i m o d e . table 58. spi c o mman d w o rd s write read 90h (1001 0000 ) 91h (1001 0001 ) 02661-a - 052 frame 1 serial bus address byte frame 2 address pointer register byte ack. by adt7316/adt7317/adt7318 ack. by adt7316/adt7317/adt7318 ack. by adt7316/adt7317/adt7318 stop by master frame 3 data byte sda (continued) scl (continued) scl sda start by master 1 0 0 1 a2 a1 a0 p 7 p6 p5 p4 p3 p2 p1 p0 9 d7 d6 d5 d4 d3 d2 d1 d0 r/w 1 9 1 9 1 f i g u re 52. i 2 c w r iti n g t o the a ddr ess p o i n t e r regi st er f o ll o w ed b y a si ngle b y t e o f d a ta to the s e l ect ed reg i st er
adt7316/adt7317/adt7318 rev. a | page 36 of 40 w r it e o p er atio n f i gur e 53 an d f i gur e 54 sh o w t h e t i min g dia g r a m s f o r a wr i te o p era t ion t o t h e ad t7316 /adt7317/adt731 8. da t a is c l oc k e d in t o t h e r e gi s t e r s o n t h e ri s i n g ed g e o f sc l k . w h en t h e cs line is hig h , t h e d i n a nd d o ut li n e s a r e in t h r e e-s t a t e m o de . o n ly w h en t h e cs g o es f r o m a hig h t o a lo w do es t h e p a r t accep t an y da t a on t h e d i n li n e . i n s p i mo de , t h e addr es s p o in t e r r e g i s t er is ca p a b l e o f a u to-i n c r e m e n t t o t h e n e xt reg i s t er in t h e r e g i s t er ma p wi t h o u t ha vi n g t o lo ad t h e addr es s p o in t e r r e g i s t er e a ch t i m e . i n f i gur e 5 4 , t h e reg i s t er addr es s p o r t io n o f t h e di a g ra m g i ves t h e f i rst r e g i st er t h a t wi l l b e wr i t t e n t o . sub s e q u e n t d a t a b y te s w i l l b e w r it te n i n to s e qu e n t i a l w r i t abl e re g i ste r s . t h e r e f ore, af te r e a ch d a t a b y te ha s b e e n w r i tte n i n to a r e g i s t er , t h e addr es s p o in t e r r e g i s t er a u t o -i n c r e m e n t s i t s v a l u e to t h e n e xt a v ai lable r e g i s t er . th e addr es s p o in t e r r e g i s t er w i l l a u to - i nc re me n t f rom 0 0 h to 3 f h a n d w i l l l o op b a ck to st ar t a l l o v er a g a i n a t 00 h w h e n i t r e a c hes 3fh. re a d o p e r a t i o n f i gur e 55 an d f i gur e 57 sh o w t h e t i min g dia g r a m s neces s a r y t o a c c o m p l i s h c o r r e c t re a d op e r a t i o ns . t o re a d b a c k f rom a r e g i s t er , f i rs t wr i t e t o t h e addr ess p o in t e r r e g i s t e r wi t h t h e a d d r e s s of t h e r e g i ste r to re a d f rom . t h i s op e r at i o n i s s h ow n i n f i gur e 53. f i gure 55 sh o w s t h e p r o c ed ur e f o r r e adin g back a sin g le b y t e o f da ta . the r e ad co mman d is f i r s t s e n t t o t h e p a r t d u r i n g t h e f i rs t eig h t clo c k c y cles, d u r i n g t h e fol l o w i n g eig h t clo c k c y cles t h e da t a con t ai n e d i n t h e r e g i st er 02661-a-053 1 sda start by master stop by master no ack. by master ack. by adt7316/adt7317/adt7318 scl 9 0 0 1 a 2 a 1 a 0 r/w d7 d6 d5 d4 d3 d2 d1 d0 frame 1 serial bus address byte frame 2 single data byte from adt7316/adt7317/adt7318 1 9 1 f i g u re 53. i 2 c r e ading a s i ng le by t e of d a t a f r o m a s e l ect ed r e g i s t er 02661-a-054 d7 d6 d5 d4 d3 d2 d1 d6 d5 d4 d3 d2 d1 d0 d0 d7 start 1 8 1 8 cs sclk din stop d7 d6 d5 d4 d3 d2 d1 d0 1 8 cs (continued) sclk (continued) data byte register address write command din (continued) f i gure 54. spi wri t ing to the address p o i n t e r re gi st er f o ll o w e d b y a si ngle b y t e o f d a ta to the s e l ect ed reg i st er 02661-a - 055 d7 din d6 d5 d4 d3 d2 d1 d6 d5 d4 d3 d2 d1 d0 d0 d7 sclk start write comma nd register address 1 8 1 8 cs stop f i gure 55. spi wri t ing to the address p o i n t e r re gi st er to se le ct a re gi ste r f o r a subse q uent re ad o p e r a t i o n
adt7316/adt7317/adt7318 rev. a | page 37 of 40 02661- a - 056 d7 d6 d5 d4 d3 d2 d1 x x x x x x x d0 x cs sclk din dout start read command data byte 1 18 1 8 x xx x x x x d6 d5 d4 d3 d2 d1 d0 xd 7 stop f i gure 56. spi re a ding a s i ng le byte of d a ta f r o m a s e l ected r e g i ster 02661-a - 057 d7 d6 d5 d4 d3 d2 d1 x x x x x x x d0 x cs sclk din dout start read comma nd da ta byte 1 1 8 1 8 x xx x x x x d6 d5 d4 d3 d2 d1 d0 xd 7 cs (continued) sclk (continued) din (continued) dout (continued) stop da ta byte 2 x x x x x x x x 1 8 d7 d6 d5 d4 d3 d2 d1 d0 f i g u re 57. spi r e ading two by t e s of dat a f r o m t w o seq u ent i al r e g i s t ers 02661-a - 058 cs spi read operation write operation f i gure 58. spi cor r ec t use of cs d u ring spi communic at ion s e l e c t e d b y t h e addre s s p o i n te r re g i ste r i s output te d on to t h e d o ut l i n e . da ta is o u t p u t t e d o n t o t h e d o ut l i ne o n t h e fal l in g e d g e o f s c lk. f i gur e 57 s h o w s t h e p r o c e d ur e w h e n re a d i n g d a t a f rom t w o s e qu e n t i a l re g i ste r s . m u lt ipl e d a t a re a d s a r e p o s s i b le in sp i in t e r f ace m o de as t h e addr ess p o in t e r r e g i s t er is a u t o -i n c r e m e n t al. the addr ess p o i n t e r r e g i s t er wi l l a u to - i nc re me n t f rom 0 0 h to 3 f h a n d w i l l l o op b a ck to st ar t a l l o v er a g a i n a t 00 h w h e n i t r e a c hes 3fh. smb u s/spi int/ int the adt7316 /adt7317/ad t7318 int/ int o u t p u t is a n in t e r r u p t l i n e t h a t sig n als an o v er -limi t / u n d er -l imi t e v e n t on a n y o f t h e m e asur em e n t cha n ne ls if t h e i n t e r r up t o n t h a t e v en t has n o t been dis a b l ed . th e ad t7316/adt7317 /adt7318 a r e a s l a v e-only de vic e a nd us e t h e smb u s/s p i int/ int a s th ei r o n l y m e an s t o sig n al o t h e r de vices t h a t a n e v e n t has o c c u r r e d .
adt7316/adt7317/adt7318 rev. a | page 38 of 40 the in t/ int p i n h a s a n o p e n - d r a i n co nf igur a t ion t h a t a l lo ws t h e ou t p u t s o f s e v e ral de vices to b e wir e d-a n d t o g e t h er w h e n th e int / int p i n is ac t i v e lo w . u s e c6 o f t h e c o n t rol c o nf ig- ura t io n 1 reg i ster t o s et t h e ac t i v e p o la r i ty o f t h e int/ int o u t p ut. th e p o w e r - u p def a u l t i s ac t i v e lo w . the int/ int o u t p u t can b e dis a b l ed o r ena b l e d b y s e t t in g c5 o f c o n t r o l c o nf igura t ion 1 r e g i st er t o a 1 or 0, r e sp e c t i v e ly . the in t/ int o u t p ut b e com e s ac t i ve w h en e i t h er t h e in t e r n al t e m p era t ur e value , t h e ext e r n al t e m p era t ur e value , o r t h e v dd val u e exce e d s t h e val u es i n t h e i r co r r es p o n d in g t hi g h /v hi g h or t low /v low r e g i st ers. th e i n t/ int o u t p u t g o es inac ti v e a g ain w h en a con v ersi o n r e s u l t i ndic a t e s t h a t al l m e asur em e n t c h a n n e ls a r e w i t h i n t h ei r tri p lim i t s , a n d w h en th e s t a t us r e g i s t er as s o c i a t e d wi t h t h e o u t- o f -limi t e v e n t is r e ad . th e tw o in t e r r u p t st a t us r e g i s t ers sh o w w h ich e v e n t ca u s e d t h e i n t/ int pi n to g o a c t i v e . the in t/ int output re qu i r e s an e x t e r n a l pu l l - u p re s i stor . t h i s ca n b e co nn e c t e d t o a v o l t a g e di f f er en t f r o m v dd p r o v id ed th a t t h e maxi m u m vol t a g e ra t i n g o f t h e i n t/ int output pi n i s not exce e d e d . th e v a l u e o f t h e p u l l - u p r e sis t o r dep e n d s on t h e a p plic a t ion b u t s h o u l d b e la rg e en o u g h t o a v o i d exces s i v e sink c u r r en ts a t t h e i n t/ int o u t p u t , w h ich can h e a t t h e chi p an d a f f e ct th e t e m p era t ur e r e ad i n g . smb u s a l er t r e sponse the in t/ int p i n b e ha v e s t h e s a m e wa y as a n smbus aler t p i n w h en t h e s m b u s/i 2 c i n t e r f ac e i s s e le c t e d . i t is an o p e n - d ra in output a n d re qu i r e s a pu l l - u p to v dd . s e v e ral i n t/ int output s ca n be wir e -and t o g e t h er s o t h a t t h e co mm o n lin e wil l g o lo w i f one or more of t h e i n t / int o u t p u t s g o es lo w . the p o la r i ty o f th e int / int p i n m u s t b e s et fo r ac t i v e lo w fo r a n u m b er o f output s to b e w i re - a n d to ge t h e r . t h e i n t / int output c a n o p era t e as an sm b a l e r t f u n c t i on. sla v e de v i ces o n t h e smb u s ca n n o r m al ly no t sig n al t o t h e mas t er t h a t t h e y wa n t t o t a l k , b u t th e sm b a l e r t fu n c ti o n a llo w s th e m t o d o s o . sm b a l e r t is us e d i n co n j u n c t io n wi t h t h e smbus gen e r a l c a l l addr ess . o n e or more i n t / int o u t p u t s can be co nn ec t e d t o a co mm o n sm b a l e r t line co nn e c t e d t o t h e mas t er . w h en sm b a l e r t line is p u l l e d lo w b y on e o f t h e de vices, t h e fol l o w in g p r o c e d ur e o c c u rs (s e e f i gu r e 59). 02661-a - 059 maste r receives smbalert start alert response address rd ack device address master sends ara and read command device sends its address no ack stop f i g u re 59. int / int re sp o n ds to smb a lert ar a 1. sm b a l e r t p ull ed l o w . 2. m a s t er i n i t i a t e s a r e ad o p era t ion an d s e n d s t h e aler t r e s p o n s e addr ess (ara = 0001 100). this is a gen e ral cal l addr ess t h a t m u st n o t b e us e d a s a sp e c if ic de vi ce ad dr ess. 3. the de v i ces w h os e int/ int o u t p u t is lo w r e s p o n ds t o th e aler t r e s p o n s e addr es s and t h e mas t er r e ads i t s de vice addr ess. si n c e t h e de vic e ad dr ess is s e ve n b i t s l o n g, a n ls b o f 1 is adde d . t h e a ddr ess o f t h e de vic e is n o w k n o w n an d i t ca n be in t e rr oga t ed i n t h e us ual w a y . 4. i f more t h a n o n e d e v i c e s i n t / int o u t p u t is lo w , t h e o n e wi t h t h e lo w e st de vice ad dr ess wi l l h a ve p r io r i t y , in acco r d an ce w i t h n o r m a l s m bus sp e c if ic a t io ns. 5. on ce t h e ad t7 316/adt7317/adt7318 has r e s p o nde d t o t h e aler t r e s p o n s e addr es s, i t wi l l r e s et i t s i n t/ int output , p r o v i d e d t h a t th e c o n d i ti o n t h a t c a u s ed th e o u t - o f - l i m i t e v en t n o lo n g er exis ts a nd t h e s t a t us r e g i s ter as s o ci a t e d wi t h t h e o u t-o f - l imi t e v e n t is r e ad . i f t h e sm b a l e r t lin e r e ma in s lo w , t h e mas t er wi l l s e nd t h e ar a a g ain. i t wi l l co n t in ue t o do t h is un til al l de vices w h os e sm b a l e r t output s we re l o w h a ve re s p o n d e d. 02661- a- 060 master receives smbalert start alert response address rd ack device address master sends ara and read command device sends its address device ack ack pec no ack stop maste r ack maste r nack device sends its pec data f i g u re 60. int / int re sp o n ds to smb a lert a r a with p a ck et e r r o r ch eck i n g (pec )
adt7316/adt7317/adt7318 rev. a | page 39 of 40 la yout consi d era t ions dig i t a l b o a r ds c a n b e ele c t r i c a l ly n o isy en vir o n m e n t s, and ca r e m u s t b e t a k e n to p r o t e c t t h e a n alog in p u ts f r o m n o is e , p a r t ic u l a r ly w h en m e as ur i n g t h e v e r y smal l v o l t a g es f r o m a re mote d i o d e s e ns or . t h e f o l l o w i n g pre c a u t i ons shou l d b e tak e n : 1. p l ace t h e ad t7 316/adt7317/adt7318 as c l os e as p o ss ibl e to t h e re mote s e ns i n g d i o d e. prov i d e d t h a t t h e w o rs t n o is e s o ur ces, s u ch as clo c k g e nera t o rs, da ta/ a dd r e s s b u se s a n d cr t s , a r e a v o i d e d , th i s dis t an c e can b e 4 in ch es t o 8 in ch es. 2. ro u te t h e d+ and d ? tra c k s c l ose t o g e th e r , i n pa ralle l , w i th gr o u n d e d g u a r d tra c k s o n ea c h s i de . p r o v id e a g r o u n d plan e u n der t h e t r acks if p o s s i b l e . 3. u s e wid e t r acks to mini mi ze i n d u c t an ce and r e d u ce n o is e pick up . a 10 mi l t r ack m i nim u m wi d t h and sp acin g is r e commende d . 02 66 1- a - 04 5 gnd d+ d? gnd 10 m i l 10 m i l 10 m i l 10 m i l 10 m i l 10 m i l 10 m i l f i gure 6 1 . a r r a ngem ent o f s i gnal t r acks 4. t r y t o minimi ze t h e n u m b er o f co p p er/s older j o in ts, w h ich can c a us e t h er m o co u p le ef fe c t s. w h er e co p p er/s older j o in ts a r e us e d , mak e s u r e t h a t t h e y a r e i n b o th th e d + a n d d ? p a th and a t t h e s a m e t e m p er - a t ur e . th er m o c o u p le ef fe c t s s h o u ld n o t b e a ma jo r p r ob lem as 1c co r r es p o n d s t o a b o u t 240 v , and t h er m o co u p l e v o l t a g es a r e ab o u t 3 v/ c o f t h e t e m p era t ur e dif f er en ce . u n les s t h er e a r e tw o t h er m o co u p les wi t h a b i g t e m p era t ur e dif f er en t i al b e tw e e n t h e m , t h er m o co u p le vol t a g es sh o u ld b e m u ch les s tha n 200 mv . 5. p l ace 0 . 1 f b y p a s s a nd 2200 p f in p u t f i l ter ca p a ci t o rs c l os e t o the adt7316/adt731 7/adt7318. 6. i f t h e dist an ce to t h e r e m o te s e n s o r is m o r e t h an 8 in ch es, t h e us e o f t h e t w is t e d p a ir ca b l e is r e com- m e nde d . this w i l l w o rk u p t o ab o u t 6 fe et t o 12 fe et. 7. f o r r e al l y lo n g dis t an ces (u p t o 100 f e et), us e s h ie lded twis t e d p a ir , s u ch as b e l d en #8451 micr o p h o n e ca b l e . c o nn ect t h e tw is t e d pa i r t o d + a n d d ? a n d th e s h ie ld t o gnd c l os e to th e adt7316 /adt7317/adt7318. l e a v e t h e r e m o te end o f t h e shi e ld u n co nn e c t e d t o a v o i d g r o u nd lo o p s. b e ca us e t h e m e as ur em e n t t e chniq u e us es s w i t ch e d c u r r en t s o ur ces, exces s i v e ca b l e and/o r f i l t er ca p a ci tan c e ca n a f f e c t t h e m e as ur e m en t. w h en usi n g lo ng ca b l es, t h e f i lter ca p a ci t o r ma y b e re d u c e d or re mo ve d. c a b l e r e sis t ance ca n als o i n t r o d uce er r o rs. s e r i es r e sis t a n ce o f 1 ? in t r o d uces a b o u t 0.5c er ro r .
adt7316/adt7317/adt7318 rev. a | page 40 of 40 outline dimensions 16 9 8 1 pin 1 sea t i n g pl a n e 0. 0 1 0 0. 0 0 4 0. 012 0. 008 0. 025 bs c 0. 01 0 0. 00 6 0. 050 0. 016 8 0 coplanarity 0.004 0. 065 0. 049 0. 069 0. 053 0. 154 bs c 0. 236 bs c compliant to jedec standards mo-137ab 0 . 193 bs c f i gure 62. 1 6 -l ead shrink sm al l o u t lin e p a ckage [qs o p ] (r q - 16) d i m e nsi o ns sh o w n in inc h es and mi ll i m eters ordering guide model 1 temperature r a nge dac re solution packag e descri ption minimum qua n tities/reel adt7318arq ?40c to +120c 8- bits 16-lead qsop n/a adt7318arq-r eel ?40c to +120 c 8-bits 16-lead qsop 2500 adt7318arq-r eel7 ?40c to +120 c 8-bits 16-lead qsop 1000 adt7317arq ?40c to +120c 10- bits 16-lead qsop n/a adt7317arq-r eel ?40c to +120 c 10-bits 16-lead qsop 2500 adt7317arq-r eel7 ?40c to +120 c 10-bits 16-lead qsop 1000 adt7316arq ?40c to +120c 12- bits 16-lead qsop n/a adt7316arq-r eel ?40c to +120 c 12-bits 16-lead qsop 2500 adt7316arq-r eel7 ?40c to +120 c 12-bits 16-lead qsop 1000 1 d e vic e s tha t ha v e da t e c o des bef o r e 0 414 ha v e an in t e r n al r e f e r e nc e of 2.25 v . d e vic e s manufac tur e d af t e r this da ta c o de ha v e the in t e r n al re f e re nce a t 2.28 v . ? 2004 a n al og devic e s , inc . a ll rig h t s r e ser v e d . t r a d em arks an d r e gist er e d tr adem ar ks ar e t h e proper t y of t h eir respec tiv e o w ners . c02661-0-6/04( a )

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